FPGA configurable logic block with multi-purpose logic/memory circuit

A lookup table circuit, comprising:

• a decoder for generating a plurality of read address signals and a plurality of write address signals in response to a first set of input signals;
• a logic/memory array including:
• a plurality of programmable elements arranged in rows and columns, each programmable element including a latch for storing a bit value, a first write transistor, an inverter, and a read transistor,
• a plurality of write word lines for transmitting write address signals generated by the decoder, the plurality of write word lines including a first write word line connected to a gate of the first write transistor of a first programmable element,
• a plurality of write bit lines including a first write bit line connected to the first write transistor of the first programmable element such that a bit value transmitted on the first write bit line is written to the latch of the first programmable element in response to a first write address signal transmitted on the first write word line,
• a plurality of read word lines for transmitting read address signals generated by the decoder, the plurality of read word lines including a first read word line connected to a gate of the read transistor of the first programmable element, and
• a plurality of read bit lines including a first read bit line connected to the read transistor of the first programmable element such that a bit value stored in the latch of the first programmable element is transmitted through the inverter and the read transistor of the first programmable element onto the first read bit line in response to a first read address signal transmitted on the first read word line;
• and
• a multiplexing circuit connected to the plurality of read bit lines for passing a bit value transmitted on one of the plurality of read bit lines in response to a second set of input signals,
• wherein the logic/memory array further comprises:
• a plurality of inverted write bit lines including a first inverted write bit line connected to a second write transistor of the first programmable element such that an inverted bit value transmitted on the first inverted write bit line is written to the latch of the first programmable element in response to the first write address signal transmitted on the first write word line;
• and
• a read/write control circuit including a first pass transistor connected between the first write bit line and the multiplexing circuit, and a second pass transistor connected between the first read bit line and the multiplexing circuit, wherein the first pass transistor is enabled to connect the first write bit line to the multiplexing circuit during a write mode, and the second pass transistor is enabled to connect the first read bit line to the multiplexing circuit during a read mode.

A programmable logic device, comprising:

• a logic/memory array including:
• a plurality of programmable elements arranged in rows and columns, each programmable element including a latch for storing a bit value, a first write transistor, an inverter, a first read transistor, and a second read transistor, the first read transistor being connected in series between the inverter and the second read transistor,
• a plurality of write word lines for transmitting a plurality of write address signals, the plurality of write word lines including a first write word line connected to a gate of the first write transistor of a first programmable element,
• a plurality of write bit lines including a first write bit line connected to the first write transistor of the first programmable element such that a bit value transmitted on the first write bit line is written to the latch of the first programmable element in response to a first write address signal transmitted on the first write word line,
• a plurality of read word lines for transmitting read address signals, the plurality of read word lines including a first read word line connected to a gate of the first read transistor of the first programmable element, and a second read word line connected to a gate of the second read transistor of the first programmable element, and
• a plurality of read bit lines including a first read bit line connected to the second read transistor of the first programmable element such that a bit value stored in the latch of the first programmable element is transmitted through the inverter and the first and second read transistors onto the first read bit line in response to a first read address signal transmitted on the first read word line and a second read address signal transmitted on the second read word line;
• a decoder for generating the plurality of write address signals in response to a first set of input signals, wherein the decoder generates a first write address signal on the first write word line in response to a first input signal and a second input signal of the first set of input signals, and also in response to a write control signal;
• and
• a hard-wired decode circuit for connecting the first set of input signals to the plurality of read word lines, wherein the hard-wired decode circuit applies the first input signal onto the first read word line as a first read address signal, and applies the second input signal onto the second read word line as a second read address signal.