Design method for compensation of process variation in CMOS digital input circuits

A digital input circuit consisting of multiple stages wherein the first stage is a Schmitt trigger circuit which contains a compensation means for lessening the effect of manufacturing process variations on the switching voltage level at the input of said digital input circuit, said compensation means being such that said digital input circuit is capable of operating at low voltage;

• wherein the first stage Schmitt trigger circuit is comprised of:
• a first P-type transistor and second P-type transistor connected in series;
• a connection from the source of the first P-type transistor to the supply voltage;
• a connection from the drain of the first P-type transistor to the source of the second P-type transistor;
• a connection from the drain of the second P-type transistor to the output node of first stage;
• a feedback loop connected from the drain of the first P-type transistor to the output node;
• a compensating N-type drain-gate shorted FET connected in parallel with the second P-type transistor where the source of said N-type FET is connected to the drain of said second P-type transistor and the drain of said N-type FET is connected to the source of said second P-type transistor;
• a first N-type transistor and second N-type transistor connected in series;
• a connection from the source of the first N-type transistor to ground;
• a connection from the drain of the first N-type transistor to the source of the second N-type transistor;
• a connection from the drain of the second N-type transistor to the output node of first stage;
• a feedback loop connected from the drain of the first N-type transistor to the output node;
• a compensating P-type drain gate shorted FET connected in parallel with the second N-type transistor where the source of said P-type FET is connected to the drain of said second N-type transistor and the drain of said P-type FET is connected to the source of said second N-type transistor.