Fail safe buffer capable of operating with a mixed voltage core
AssigneeLucent Technologies Inc.
InventorBernard L. Morris
Life of this patent
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Abstract
A voltage blocking circuit is disclosed, useable in a buffer portion of an integrated circuit, for a buffer portion of an IC chip that operates from a power supply different from the power supply that powers the core logic; however, the buffer remains in a high impendence state, regardless of whether or not power is supplied to the core logic.
Claims12
An integrated circuit (IC) having a buffer receiving power from a first power supply and core logic receiving power from a second power supply, comprising:
- a core-voltage blocking circuit coupled to said second power supply, wherein an output of said IC is in a high impedance state when said second power supply is not applied to said core logic.
An integrated circuit (IC) having a buffer receiving power from a first power supply and core logic receiving power from a second power supply, comprising:
- means for maintaining an output of said IC in either a high-impedance or normal state regardless of whether power is supplied from said second power supply to said core logic.
A method of operating an IC having a buffer receiving power from a first power supply and core logic receiving power from a second power supply, comprising the steps of:
- passing a signal from said core logic to an output of said IC when said second power supply is supplying power to said core logic;
- blocking signals from said core logic to said output of said IC when said second power supply is not supplying power to said core logic;
- and
- pulling down the output of said core-voltage blocking circuit when said second power supply is not supplying power to said core logic.
Dependencies are inferred from the claim text.