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US 6,184,585 B2Granted
Co-packaged MOS-gated device and control integrated circuit
AssigneeInternational Rectifier Corporation
InventorsRoberto Martinez, Chuan Cheah
Life of this patent
Estimating the term…
Abstract
An electronic package for an electronic device includes a substrate. A power transistor die has a lower surface and a upper surface, and the lower surface of the power transistor die is mounted on the substrate. A control circuit for controlling the power transistor is mounted to the upper surface of the power transistor die using an insulating epoxy.
Claims20
A semiconductor device comprising:
- a conductive lead frame having at least one pad area;
- a first semiconductor die comprising an MOS-gated semiconductor device having opposing surfaces, a first one of said opposing surfaces having at least one electrode being disposed in electrical contact with said one pad area, a second one of said opposing surfaces having at least a gate electrode;
- and
- a second semiconductor die comprising a control IC having opposing surfaces, a first one of said opposing surfaces of said control IC being disposed in contact with but electrically insulated from said second opposing surface of said MOS-gated device, a second one of said opposing surfaces of said control IC having at least one electrode that is electrically coupled to said gate electrode of said MOS-gated semiconductor device.
1 more element
A semiconductor device comprising:
- a conductive lead frame having at least first and second pad areas;
- a first semiconductor die comprising a first MOS-gated semiconductor device having opposing surfaces, a first one of said opposing surfaces having at least one electrode being disposed in contact with said first pad area, a second one of said opposing surfaces having at least a gate electrode and another electrode;
- a second semiconductor die comprising a control IC having opposing surfaces, a first one of said opposing surfaces of said control IC being disposed in contact with but electrically insulated from said second opposing surface of said first MOS-gated device, a second one of said opposing surfaces of said control IC having at least one electrode that is electrically coupled to said gate electrode of said first MOS-gated semiconductor device;
- a third semiconductor die comprising a diode having opposing surfaces, a first one of said opposing surfaces of said diode being disposed in electrical contact with said first main pad area, a second one of said opposing surfaces having at least one electrode that is electrically coupled with said another electrode of said first MOS-gated semiconductor device;
- and
- a fourth semiconductor die comprising an MOS-gated semiconductor device having opposing surfaces, a first one of said opposing surfaces of said second MOS-gated semiconductor device having at least one electrode being disposed in electrical contact with said second pad area, a second one of said opposing surfaces having at least a gate electrode and another electrode, said gate electrode of said second MOS-gated semiconductor device being electrically coupled to said control IC, and said another electrode of said second MOS-gated semiconductor device being electrically coupled to said first pad area.
3 more elements
Dependencies are inferred from the claim text.