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US 6,184,575 B2Granted
Ultra-thin composite package for integrated circuits
AssigneeNational Semiconductor Corporation
InventorsSatya Chillara, Shahram Mostafazadeh
Life of this patent
Estimating the term…
Abstract
An ultra-thin composite package for integrated circuits including a metal base with a cavity to support a die with a molded plastic cap cooperating with the base to encapsulate the die. A lead frame having a thinned inner portion or lead tip areas may also be used to further reduce the package thickness. Package thicknesses of about 20 mils (0.5 mm) or less can be readily achieved using this structure combination.
Claims14
A semiconductor device package, comprising:
- (a) a metal base having a top surface and a cavity formed in the top surface;
- (b) a lead frame having a plurality of leads, the lead frame being supported by the top surface of the base;
- (c) an insulating layer positioned between the lead frame and the top surface of the base, the insulating layer being arranged to electrically insulate the lead frame from the base;
- (d) an integrated circuit die received within the base cavity and electrically coupled to the lead frame;
- (e) a plastic cap molded over the top surface of the metal base, the die and an inner portion of lead frame, the cap cooperating with the base to encapsulate the die wherein the plastic cap is in direct contact with the integrated circuit die;
- and
- (f) wherein the lead frame includes a lead tip portion having a first thickness that is under the cap and a pin portion having a second thickness that is outside the cap, the lead tip portion being thinner than the pin portion.
4 more elements
A semiconductor device package, comprising:
- (a) a metal base having a top surface and a cavity formed in the top surface, wherein the metal base thickness is less than or equal to approximately 12 mils;
- (b) a lead frame having a plurality of leads, the lead frame being supported by the top surface of the base;
- (c) an insulating layer positioned between the lead frame and the top surface of the base, the insulating layer being arranged to electrically insulate the lead frame from the base;
- (d) an integrated circuit die received within the base cavity and electrically coupled to the lead frame, wherein the die thickness is in the range of approximately 6 to 10 mils;
- (e) a plastic cap molded over the top surface of the metal base, the die and an inner portion of lead frame, the cap cooperating with the base to encapsulate the die wherein the plastic cap is in direct contact with the integrated circuit die and wherein the molded plastic cap is in the range of approximately 6-12 mils thick.
2 more elements
A semiconductor device package, comprising:
- (a) a metal base having a top surface and a cavity formed in the top surface;
- (b) the lead frame having a plurality of leads, the lead frame being supported by the top surface of the base and including a lead tip portion having a first thickness and a pin portion having a second thickness, the lead tip portion being thinner than the pin portion;
- (c) an insulating layer positioned between the lead frame and the top surface of the base, the insulating layer being arranged to electrically insulate the lead frame from the base;
- (d) an integrated circuit die received within the base cavity and electrically coupled to the lead frame;
- (e) a cap molded directly over the top surface of the metal base, the die and an inner portion of lead frame having the first thickness, the cap being arranged such that the cap does not overlap any portion of the lead frame having the second thickness, the cap cooperating with the base to encapsulate the die.
2 more elements
Dependencies are inferred from the claim text.