Multi-capacitance lead frame decoupling device

A packaged integrated circuit device assembly comprising:

• an integrated circuit chip having at least one integrated circuit therein, said integrated circuit chip having a first active surface having, in turn, at least one contact pad arranged thereon and having a second surface;
• an upper conductive planar lead frame member having an upper surface mounted to said second surface of said integrated circuit chip using an intervening electrically insulative adhesive, and having a lower surface;
• a lower conductive planar lead frame member having an upper surface mounted to the lower surface of said upper conductive planar lead frame member using a thin intervening layer of dielectric material whereby capacitance results, said lower conductive planar lead frame member subdivided into a plurality of portions, at least one portion of said plurality of portions having an exposed tab connected to said at least one integrated circuit of said integrated circuit chip, said lower conductive planar lead frame member cooperating with said upper conductive planar lead frame member;
• at least one lead of a plurality of leads connecting said at least one contact pad to at least one lead finger;
• and
• at least one other lead of said plurality of leads connected to at least one tab of said lower conductive planar lead frame member.

An packaged integrated circuit device assembly comprising:

• a housing;
• an integrated circuit chip located in said housing, said integrated circuit chip having at least one integrated circuit therein, said integrated circuit chip having a first surface having, in turn, at least one contact pad arranged thereon and having a second surface, said at least one integrated circuit of said integrated circuit chip subject to transient electrical coupling and noise generation;
• an upper conductive planar lead frame member having an upper surface mounted to said second surface of said integrated circuit chip using an intervening electrically insulative adhesive, and having a lower surface, said upper conductive planar lead frame member subdivided into multiple portions, at least one portion of said multiple portions having an exposed tab connected to said at least one integrated circuit;
• a lower conductive planar lead frame member having an upper surface mounted to the lower surface of said conductive planar upper lead frame member using a thin intervening layer of dielectric material, said conductive planar lead frame lower lead frame member cooperating with said upper conductive planar lead frame member;
• at least one lead of a plurality of leads connecting said at least one contact pad to at least one lead finger;
• and
• at least one other lead of said plurality of leads connected to at least one tab of said upper conductive planar lead frame member and across portions of said at least one integrated circuit of said integrated circuit chip subject to transient coupling and noise generation.

A packaged integrated circuit device assembly comprising:

• a housing;
• an integrated circuit chip in said housing, said integrated circuit chip having an integrated circuit therein, said integrated circuit chip having a first surface having, in turn, a plurality of contact pads arranged thereon and having a second surface, said integrated circuit of said integrated circuit chip subject to transient electrical coupling and noise generation;
• an upper conductive planar lead frame member having an upper surface mounted to said second surface of said integrated circuit chip using an intervening electrically insulative adhesive, and having a lower surface;
• a lower conductive planar lead frame member having an upper surface mounted to the lower surface of said upper conducive planar lead frame member using a thin intervening layer of dielectric material whereby capacitance results, said lower conductive planar lead frame member subdivided into multiple portions, at least one of said multiple portions having an exposed tab connected to said integrated circuit and having tailored operating capacitance/frequency characteristics in cooperation with the upper conductive planar lead frame member;
• at least one lead connecting at least one contact pad of said plurality of contact pads to at least one lead finger;
• and
• at least one other lead connected to an at least one tab of said lower conductive planar lead frame member and across portions of said integrated circuit of said integrated circuit chip subject to transient coupling and noise generation.

An packaged integrated circuit device assembly comprising:

• a housing;
• an integrated circuit chip in said housing, said integrated circuit chip having an integrated circuit therein, said integrated circuit chip having a first surface having, in turn, a plurality of contact pads arranged thereon and having a second surface for mounting said integrated circuit chip, said integrated circuit of said integrated circuit chip subject to transient electrical coupling and noise generation;
• an upper conductive lead frame member having an upper surface mounted to said second surface of said integrated circuit chip using an intervening electrically insulative adhesive, and a lower surface;
• a lower conductive lead frame member having an upper surface mounted to the lower surface of said upper conductive planar lead frame member using a thin intervening layer of dielectric material whereby capacitance results;
• leads connecting some of said plurality of contact pads to lead fingers;
• leads connected to said upper and lower conductive lead frame members and across portions of said integrated circuit of said integrated circuit chip subject to transient coupling and noise generation;
• wherein one of said upper and lower conductive lead frame members is subdivided into multiple portions, each of said multiple portions having at least one exposed tab connected to said integrated circuit and having tailored operating capacitance/frequency characteristics in cooperation with the non-subdivided lead frame member.

A method for making an integrated circuit package having a semiconductor chip having an active surface and a support surface, said method comprising:

• forming a multi-level conductive lead frame with a lower lead frame portion and an upper lead frame portion partially coextensive therewith, said upper and lower lead frame portions each having upper and lower surfaces, said upper surface of said upper lead frame portion configured to be bonded to the support surface of said semiconductor chip, said upper lead frame portion subdivided into a plurality of units having at least one outwardly extending conductive tab, one of said lower and upper lead frame portions having centrally directed inner leads;
• providing a dielectric material;
• joining the upper surface of the lower lead frame portion to the lower surface of one of the plurality of units of said subdivided upper lead frame portion using an intervening layer of said dielectric material, whereby each of the plurality of units formed by the upper lead frame portion and said intervening dielectric material layer comprising a capacitor;
• providing an insulative material;
• bonding the support surface of said semiconductor chip to the upper surface of the subdivided upper lead frame portion using said insulative material;
• lancing the lead frame portions to singulate inner leads therefrom;
• bonding conductive wires between wire bond pads on the active surface of the semiconductor chip and the inner leads, the at least one conductive tab of the subdivided upper lead frame portion, and the lower lead frame portion;
• encapsulating the semiconductor chip, inner leads, a plurality of capacitors, and conductive wires in a package;
• and
• lancing external lead portions to form outer leads for connecting the integrated circuit package to an electronic apparatus.