Integrated circuit dies including thermal stress reducing grooves and microelectronic packages utilizing the same

An integrated circuit comprising:

• an integrated circuit die including first and second opposing faces;
• a plurality of spaced apart bonding regions on the first face;
• and
• a plurality of grooves in the second face, a respective one of which extends between a respective pair of adjacent spaced apart bonding regions.

An integrated circuit comprising:

• an integrated circuit die including first and second opposing faces;
• a plurality of spaced apart bonding regions on the first face;
• and
• at least one groove in the second face;
• wherein the integrated circuit die is about 0.6 mm thick between the first and second opposing faces and wherein the at least one groove is about 0.5 mm deep.

A microelectronic package comprising:

• an integrated circuit die including first and second opposing faces, a plurality of spaced apart bonding regions on the first face, and at least one groove in the second face that allows the die to flex upon application of stress to the bonding regions due to thermal cycling of the integrated circuit die, compared to absence of the at least one groove;
• a plurality of solder bumps, a respective one of which is mechanically attached to a respective bonding region;
• and
• a mounting substrate that is mechanically attached to the plurality of solder bumps, opposite the bonding regions.

A microelectronic package comprising:

• an integrated circuit die including first and second opposing faces, a plurality of spaced apart bonding regions on the first face, and
• a plurality of grooves in the second face, a respective one of which extends between a respective pair of adjacent spaced apart bonding regions;
• a plurality of solder bumps, a respective one of which is mechanically attached to a respective bonding region;
• and
• a mounting substrate that is mechanically attached to the plurality of solder bumps, opposite the bonding regions.

A microelectronic package comprising:

• an integrated circuit die including first and second opposing faces, a plurality of spaced apart bonding regions on the first face, and at least one groove in the second face;
• a plurality of solder bumps, a respective one of which is mechanically attached to a respective bonding region;
• and
• a mounting substrate that is mechanically attached to the plurality of solder bumps, opposite the bonding regions;
• wherein the integrated circuit die is about 0.6 mm thick between the first and second opposing faces and wherein the at least one groove is about 0.5 mm deep.