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US 6,184,558 B2Granted
Comparator having reduced offset voltage
AssigneeSeiko Instruments Inc.
InventorsKenji Kitamura, Mika Shiiki, Jun Osanai
Life of this patent
Estimating the term…
Abstract
An object of the invention is to reduce an offset voltage to realize a small occupying area in a comparator using MOS type transistors. The invention is characterized in that impurities are introduced into channel areas of MOS type transistors, and mobility of the MOS type transistor on a load side is smaller than mobility of the MOS type transistor on a differential side, and a mutual conductance gm of the MOS type transistor on the load side is smaller than a mutual conductance gm of the MOS type transistor on the differential side.
Claims17
A comparator circuit comprising:
- a load side having a load side MOS transistor;
- and a differential side having a differential side MOS transistor;
- wherein a mutual conductance (gm) of the load side MOS transistor on the load side is smaller than a mutual conductance (gm) of the differential side MOS transistor on the differential side.
Dependencies are inferred from the claim text.