Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device

A nonvolatile semiconductor memory device comprising:

• a substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level and a step side region linking the first and second surface regions together;
• a channel region formed in the first surface region of the substrate;
• source and drain regions formed to interpose the channel region therebetween;
• an insulating film formed on the surface of the substrate;
• a floating gate formed on the insulating film;
• and
• a control gate being capacitively coupled to the floating gate,
• wherein the insulating film includes a first part formed on the first surface region, and a second part formed on the step side region and the second surface region, and
• wherein the control gate is formed on the first part of the insulating film, and
• wherein part of the floating gate faces the step side region through the second part of the insulating film, and another part of the floating gate faces the first surface region through the first part of the insulating film, and
• wherein a boundary between the floating gate and the control gate is located at a position away from the step side region toward the source region, and
• wherein the channel region includes a high-concentration impurity region being located close to the step side region, said high-concentration impurity region not covering a corner portion between the second surface region and the step side region, and said high-concentration impurity region having an impurity concentration higher than that of the channel region in a part thereof adjacent to the source region.

A nonvolatile semiconductor memory device comprising:

• a substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level and a step side region linking the first and second surface regions together;
• a channel region formed in the first surface region of the substrate;
• source and drain regions formed to interpose the channel region therebetween;
• an insulating film formed on the surface of the substrate;
• a floating gate formed on the insulating film;
• and
• a control gate being capacitively coupled to the floating gate,
• wherein the insulating film includes a first part formed on the first surface region, and a second part formed on the step side region and the second surface region, and
• wherein the control gate is formed on the first part of the insulating film, and
• wherein part of the floating gate faces the step side region through the second part of the insulating film, and another part of the floating gate faces the first surface region through the first part of the insulating film, and
• wherein a boundary between the floating gate and the control gate is located at a position away from the step side region toward the source region, and
• wherein an inversion layer is formed in the step side region during the operation of the device, and
• wherein an extremely-low-concentration impurity layer is formed in the step side region.