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US 6,184,539 B2Granted
Static memory cell and method of forming static memory cell
AssigneeMicron Technology, Inc.
InventorsJeff Zhiqiang Wu, Joseph Karniewicz
Life of this patent
Estimating the term…
Abstract
A static memory cell having no more than three transistors. A static memory cell comprises a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain; and alternating layers of insulative and conductive material formed proximate the source, including two conductive layers and two insulative layers, one of the insulative layers being in junction relation to the source.
Claims30
A static memory cell comprising:
- a semiconductor substrate of a first conductivity type;
- a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type;
- a transistor formed relative to the substrate over the buried layer, the transistor having a channel of the second conductivity type, and the transistor having a gate, a memory node, and a digit line node;
- and
- alternating layers of insulative and conductive material formed relative to the memory node to form, in combination with the memory node, a resonant tunnel diode.
2 more elements
A static memory cell comprising:
- a semiconductor substrate of a first conductivity type;
- a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type;
- a transistor formed relative to the substrate over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain;
- and
- alternating layers of insulative and conductive material formed relative to the source, including conductive layers and insulative layers, one of the insulative layers being in junction relation to the source.
2 more elements
A static memory cell comprising:
- a semiconductor substrate;
- a transistor formed in the substrate, the transistor including a gate, a first n+ region having a depth in the substrate, and a second n+ region having a depth in the substrate greater than the depth of the first n+ region;
- an n+ buried layer below the second n+ region;
- and
- alternating layers of insulative and conductive material formed relative to the second n+ region, including two conductive layers and two insulative layers, and defining, in combination with the second n+ region, a resonant tunnel diode.
2 more elements
A static memory cell comprising:
- a semiconductor substrate;
- a transistor formed in the substrate, the transistor including a gate, a first p+ region having a depth in the substrate, and a second p+ region having a depth in the substrate greater than the depth of the first p+ region;
- a p+ buried layer below the second p+ region;
- and
- alternating layers of insulative and conductive material formed relative to the second p+ region, including two conductive layers and two insulative layers, and forming, in combination with the second p+ region, a resonant tunnel diode.
2 more elements
A static memory cell comprising:
- a p-type semiconductor substrate having an average p-type dopant concentration of at least 1×1016 ions/cm3 and being configured to be connected to a first voltage;
- a buried n-type diffusion layer in the substrate, the n-type layer having an average n-type dopant concentration of at least 1×1019 ions/cm3 and being configured to be connected to a second voltage lower than the first voltage;
- an n-channel transistor formed relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having an average n-type dopant concentration of at least 1×1019 ions/cm3 and the drain having an average n-type dopant concentration of at least 1×1019 ions/cm3;
- and
- alternating layers of insulative and conductive material formed relative to the source, including two conductive layers and two insulative layers, and defining, in combination with the source, a resonant tunnel diode, the layers including a lower insulative layer in junction relation to the source and an upper conductive layer defining a terminal for the resonant tunnel diode, the terminal for the resonant tunnel diode being configured to be connected to a third voltage higher than the first voltage.
2 more elements
A static memory cell comprising:
- an n-type semiconductor substrate having an average n-type dopant concentration of at least 1×1016 ions/cm3 and being configured to be connected to a first voltage;
- a buried p-type diffusion layer in the substrate, the p-type layer having an average p-type dopant concentration of at least 1×1019 ions/cm3 and being configured to be connected to a second voltage greater than the first voltage;
- a p-channel transistor formed relative to the substrate over the buried p-type layer, the p-channel transistor having a source, a gate, and a drain, the source having an average p-type dopant concentration of at least 1×1019 ions/cm3 and the drain having an average p-type dopant concentration of at least 1×1019 ions/cm3;
- and
- alternating layers of insulative and conductive material formed relative to the source, including two conductive layers and two insulative layers, and forming, in combination with the source, a resonant tunnel diode, the layers including a lower insulative layer in junction relation to the source and an upper conductive layer forming a terminal for the resonant tunnel diode, the terminal for the resonant tunnel diode being configured to be connected to a third voltage lower than the first voltage.
2 more elements
A static memory cell comprising:
- an n-channel MOSFET having a drain, gate, and source;
- a npn transistor having a base, a collector, and an emitter;
- and
- alternating layers of conductive and insulative material defining, in combination with the source of the MOSFET, a resonant tunnel diode, the resonant tunnel diode having an anode configured to be connected to a first voltage and a cathode connected to the collector of the npn transistor.
1 more element
Dependencies are inferred from the claim text.