Method to prevent delamination of spin-on-glass and plasma nitride layers using ion implantation

A method of forming an integrated circuit device comprising:

• providing semiconductor device structures in and on a semiconductor substrate wherein conductive connections are planned between said device structures and planned conductive traces overlying a planned interlevel dielectric layer;
• depositing an insulating oxide layer overlying said device structures;
• coating a spin-on-glass layer overlying said insulating oxide layer wherein said spin-on-glass is one of a group composed of:
• polysiloxane-based and silicate-based compounds;
• drying said spin-on-glass layer;
• ion implanting said spin-on-glass layer with silicon ions to form an amorphous, silicon rich, adhesion layer at the top surface of said spin-on-glass layer wherein said adhesion layer is formed to a depth of between about 1,000 Angstroms and 2,000 Angstroms;
• curing said spin-on-glass layer;
• depositing a first plasma-enhanced silicon nitride layer overlying said adhesion layer of said spin-on-glass and thereby completing said interlevel dielectric layer;
• etching through said first plasma-enhanced silicon nitride layer, said adhesion layer, said spin-on-glass layer, and said insulating oxide layer to the top surfaces of said semiconductor device structures where defined by a photolithographic mask and thereby forming via openings;
• depositing a conductive layer overlying said first plasma-enhanced silicon nitride layer and filling said via openings and thereby forming said conductive connections;
• etching said conductive layer where defined by photolithographic mask and thereby forming said conductive traces;
• depositing a second plasma-enhanced silicon nitride layer overlying said conductive traces and said first plasma-enhanced silicon nitride layer;
• and
• completing said integrated circuit device.

A method of forming an integrated circuit device comprising:

• providing semiconductor device structures in and on a semiconductor substrate wherein conductive connections are planned between said device structures and planned conductive traces overlying a planned interlevel dielectric layer;
• depositing an insulating oxide layer overlying said device structures;
• coating a spin-on-glass layer overlying said insulating oxide layer wherein said spin-on-glass is one of a group composed of:
• polysiloxane-based and silicate-based compounds;
• drying said spin-on-glass layer;
• ion implanting said spin-on-glass layer with silicon ions to form an amorphous, silicon rich, adhesion layer at the top surface of said spin-on-glass layer wherein said adhesion layer is formed to a depth of between about 2,000 Angstroms and 3,000 Angstroms and wherein said ion implanting is performed at a dose concentration of between about 1.0×103 atoms/cm3 and 1.0×105 atoms/cm3 and an implant energy of between about 50 KeV and 250 KeV;
• curing said spin-on-glass layer;
• depositing a first plasma-enhanced silicon nitride layer overlying said adhesion layer of said spin-on-glass and thereby completing said interlevel dielectric layer;
• etching through said first plasma-enhanced silicon nitride layer, said adhesion layer, said spin-on-glass layer, and said insulating oxide layer to the top surfaces of said semiconductor device structures where defined by a photolithographic mask and thereby forming via openings;
• depositing a conductive layer overlying said first plasma-enhanced silicon nitride layer and filling said via openings and thereby forming said conductive connections;
• etching said conductive layer where defined by photolithographic mask and thereby forming said conductive traces;
• depositing a second plasma-enhanced silicon nitride layer overlying said conductive traces and said first plasma-enhanced silicon nitride layer;
• and
• completing said integrated circuit devices.