Back to results
US 6,184,094 B2Granted
Method for producing semiconductor device
AssigneeNEC Corporation
InventorYoshiro Goto
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeNEC Corporation
InventorYoshiro Goto
Estimating the term…
Producing method for a semiconductor device in which, for producing CMOS transistors of plural sorts, for example, dual power source transistors, having an added ROM unction, the number of times of ion implantation and resist pattern formation can be reduced to reduce the number of producing process steps. In producing a semiconductor device comprised of five sorts of MOS transistors, namely thin-film CMOS transistors (area A of FIG. 1), thick-film CMOS transistors (area B of FIG. 1) and an ROM code transistor (area C of FIG. 1), ion implantation for forming an inversion layer (13 of FIG. 1) on a channel surface of the ROM code transistor and the ion implantation for adjusting threshold value voltage of P channel of the CMOS transistor are carried out in the same process step (process (d) of FIG. 5). Also, the ion implantation for adjusting threshold value voltage of N channel of the thin-film CMOS transistor is effected using a resist pattern (4d of FIG. 6(g)) for the formation of a gate oxide film of the thin-film C MOS transistor (step (g) of FIG. 6).
A method for producing a semiconductor device having, as constituent elements, at least five sorts of MOS transistors including a thin-film CMOS transistor, a thick-film CMOS transistor and a ROM code transistor, comprising:
A method for producing a semiconductor device having, as constituent elements, at least five sorts of MOS transistors including a thin-film CMOS transistor, a thick-film CMOS transistor and a ROM code transistor, comprising:
A method for producing a semiconductor device comprising:
A method for producing a semiconductor device comprising:
A method for producing a semiconductor device comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
No related US applications are recorded in the indexed filing history.
Peripheral circuit regions: of memory structures of the ROM only type
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their doped wells
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
Term ended 27 Jan 2020 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
This invention relates to a method for producing a semiconductor device and, more particularly, to a method for producing a semiconductor device made up of plural MOS transistors including ROM code transistors.
In keeping pace with progress in the fine machining technology in the manufacture of semiconductor devices, the tendency is towards higher integration and higher speed of semiconductor devices, in particular the complementary insulated gate semiconductor devices (CMOS). For coping with this tendency, the driving power source is becoming lower. That is, while the power source of 5 V is routinely used, a composite transistor device partly incorporating built-in MOS transistors of a power voltage system with 3.3 V or 2.5 V or less is currently manufactured.
In such MOS transistors, it is necessary to form an element with a different film thickness of a gate insulating film because of the difference in the gate withstand voltage or in order to obtain desired electrical properties. Since the gate insulating films need to be of different film thicknesses, it is necessary to implant ions separately from one element of a given sort to another to control the concentration of impurities.
FIG. 1 is a cross-sectional view for illustrating the structure of a semiconductor device in which the thin-film and thick-film dual power source CMOS transistors co-exist with a ROM code transistor.
FIGS. 2(a)-2(d) are cross-sectional views for illustrating the process schematically illustrating a portion of the producing method of a semiconductor device according to a first embodiment of the present invention.
FIGS. 3(e)-3(h) are cross-sectional views for illustrating the process schematically illustrating another portion of the producing a method of a semiconductor device according to the first embodiment of the present invention.
The present invention provides, in a preferred embodiment, a producing method for producing a semiconductor device comprised of five sorts of MOS transistors, namely thin-film CMOS transistors (area A of FIG. 1), thick-film CMOS transistors (area B of FIG. 1) and a ROM code transistor (area C of FIG. 1), an ion implantation for forming an inversion layer (13 of FIG. 1) on a channel surface of the ROM code transistor and an ion implantation for adjusting the threshold value voltage of the P channels of the thin-film CMOS transistors are carried out in the same process step (process (d) of FIG. 5). Also, the ion implantation for adjusting the threshold value voltage of the N channels of the thin-film CMOS transistors is effected using a resist pattern (4d of FIG. 6(g)) for the formation of a gate oxide film of the thin-film CMOS transistor (step (g) of FIG. 6). In this manner, concentrations of impurities on the channel surfaces of the five sorts of the MOS transistors are adjusted four times for of ion implantation operations and four times for resist pattern formation operations, to reduce the number of process steps.
For further elucidating the above-mentioned preferred embodiments of the present invention, examples of the present invention will be explained in more detail by referring to the drawings.
Referring first to FIGS. 1 to 4, the producing method for a semiconductor device according to a first example of the present invention is explained. FIG. 1 shows, in cross-section, the structure of a semiconductor device in which dual power source CMOS transistors and a sole ROM code transistor exist together and FIGS. 2 to 4 are cross-sectional views for illustrating the producing method of the semiconductor device. Although shown in the three views of FIGS. 2 to 4, the process steps represent a sole sequence of the producing process.