Self-aligned contact for trench DMOS transistors

A method forforming a self-aligned contact for a trench DMOS transistor, comprising:

• providing a semiconductor substrate;
• etching a trench into said semiconductor substrate at a selected location on the surface of said semiconductor substrate;
• forming a first dielectric layer that covers said semiconductor substrate and walls of said trench;
• forming a plug in said trench, wherein said plug is below said trench for about 0.2 to 0.3 micron;
• forming a second dielectric layer on said plug, which comprises a step of oxidizing said plug so that said second dielectric layer is formed to fill the portion of said trench from which said plug is recessed;
• forming a silicon nitride layer over said second dielectric layer and said surface of said semiconductor substrate;
• forming an inter-layer dielectric (ILD) layer over said silicon nitride layer;
• patterning said ILD layer and said silicon nitride layer to expose pre-selected regions on said surface of said semiconductor substrate;
• and
• forming a conductive layer over said second dielectric layer, remaining portions of said ILD layer, and said surface of said semiconductor substrate for ohmic contact regions.

A method forforming a self-aligned contact for a trench DMOS transistor, comprising:

• providing a semiconductor substrate;
• etching a trench into said semiconductor substrate at a selected location on the surface of said semiconductor substrate;
• forming a linear oxide layer with a thickness of approximately 300 to 1200 Angstroms;
• stripping off said linear oxide layer by a wet etching process to reduce sidewall defects of said trench and get a smooth trench sidewall;
• forming a plug in said trench, wherein said plug is below said trench for about 0.2 to 0.3 micron;
• forming a second dielectric layer on said plug, which comprises a step of oxidizing said plug so that said second dielectric layer is formed to fill the portion of said trench from which said plug is recessed;
• forming a silicon nitride layer over said second dielectric layer and said surface of said semiconductor substrate;
• forming an ILD layer over said silicon nitride layer;
• patterning said ILD layer and said silicon nitride layer to expose pre-selected regions on said surface of said semiconductor substrate;
• and
• forming a conductive layer over said second dielectric layer, remaining portions of said ILD layer, and said surface of said semiconductor substrate for ohmic contact regions.