Method of fabricating a capacitor under bit line DRAM structure using contact hole liners

A method of fabricating a DRAM capacitor structure, on a semiconductor substrate, featuring an upper capacitor plate structure, defined during bit line, capacitor, and substrate contact hole openings, and featuring silicon nitride spacers on the sides of all contact holes, comprising the steps of:

• providing silicon nitride capped, polycide gate structures, with silicon nitride sidewall spacers, on an a silicon dioxide gate insulator layer, with source/drain regions located in a region of said semiconductor substrate not covered by said silicon nitride capped, polycide gate structures;
• depositing a first silicon oxide layer;
• planarizing said first silicon oxide layer;
• forming self-aligned contact openings, in said first silicon oxide layer, with each self-aligned contact opening exposing a source/drain region, located between said silicon nitride capped polycide gate structures;
• forming a first polysilicon plug structure, in a first self-aligned contact opening, and forming a second polysilicon plug structure, in a second self-aligned contact opening;
• depositing a first silicon nitride layer;
• depositing a second silicon oxide layer;
• forming a first storage node opening, in said second silicon oxide layer, and in said first silicon nitride layer, exposing the top surface said first polysilicon plug structure, and forming a second storage node opening, in said second silicon oxide layer, and in said first silicon nitride layer, exposing a portion of the top surface of said first silicon oxide layer;
• forming a first storage node structure, in said first storage node opening, contacting underlying first polysilicon plug structure, and forming a second storage node structure, in said second storage node opening, overlying said first silicon oxide layer, resulting a narrow space between said first storage node structure, and said second storage node structure, exposing a portion of said first silicon nitride layer;
• forming a capacitor dielectric layer;
• depositing a polysilicon layer;
• depositing a third silicon oxide layer;
• using a first opening, in a photoresist shape, to form a bit line contact hole opening, in a region not covered by storage node structures, anisotropically in said third silicon oxide layer, isotopically in said polysilicon layer, and anisotropically in said capacitor dielectric layer, and in said first silicon nitride layer, exposing the top surface of a second polysilicon plug structure, and featuring an undercut region, in said polysilicon layer;
• using a second opening, in said photoresist shape, to form a capacitor contact hole opening, anisotropically in said third silicon oxide layer, isotopically in a top portion of said polysilicon layer, located in said narrow space, exposing a bottom portion of said polysilicon layer, in said narrow space, and anisotropically in said capacitor dielectric layer, exposing a portion of said first storage node structure;
• using a third opening, in said photoresist shape, to form a substrate contact hole opening, in a region not covered by said storage node structures, anisotropically in said third silicon oxide layer, isotopically in said polysilicon layer, creating an undercut region in said polysilicon layer, and anisotropically in said in said capacitor dielectric layer, in said first silicon nitride layer, and in said first silicon oxide layer, exposing a portion of said semiconductor substrate;
• using a fourth opening, in said photoresist shape, as an etch mask, to define said upper capacitor plate structure, in a region not covered by said storage node structures, via anisotropic etching of said third silicon oxide layer, isotropic etching of said polysilicon layer, and anisotropic etching of said capacitor dielectric layer, first silicon nitride layer, and of said first silicon oxide layer, creating said DRAM capacitor structure comprised of said upper plate capacitor structure, capacitor dielectric layer, and a lower capacitor plate structure, with said lower capacitor plate comprised of said first storage node structure, and said second storage node structure, connected by said bottom portion of said polysilicon layer, located in said narrow space;
• depositing a second silicon nitride layer;
• performing an anisotropic dry etching procedure to create silicon nitride spacers on the sides of said bit line contact hole, said capacitor contact hole, and said substrate contact hole, with thick silicon nitride spacers located in undercut regions of said polysilicon layer, in said bit line contact hole, and in said substrate contact hole;
• and
• forming a bit line contact plug structure, in said bit line contact hole opening, a capacitor contact plug structure, in said capacitor contact hole opening, and forming a substrate contact plug structure, in said substrate contact hole opening.