Method of fabrication a self-aligned polysilicon/diffusion barrier/oxygen stable sidewall bottom electrode structure for high-K DRAMS
AssigneeTexas Instruments Incorporated
InventorsDarius Crenshaw, Scott Summerfelt
Life of this patent
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Abstract
The capacitor (12) comprises a HDC dielectric (40) and upper (44) and lower (32-36) electrodes. The lower electrode comprises a polysilicon base (32), a diffusion barrier (34) on the sidewalls of the polysilicon base (32) and an oxygen stable material (36) on the sidewalls adjacent the diffusion barrier (34) and separated from the polysilicon base (32) sidewalls by the diffusion barrier (34). The oxygen stable material (36) is formed on the sidewalls by a deposition and either etchback or CMP process rather than by a patterned etch. The HDC dielectric (40) is then formed adjacent the oxygen stable material (36).
Claims23
A method for forming a high dielectric constant (HDC) capacitor comprising the steps of:
- forming a temporary dielectric layer over a structure for which the capacitor is desired;
- forming a pattern over the temporary dielectric layer, said pattern exposing portions of the temporary dielectric layer over a storage node area where a bottom electrode of the capacitor is desired;
- etching said temporary dielectric layer using said pattern to remove said temporary dielectric layer in said storage node area;
- removing said pattern;
- forming a conductive base in said storage node area;
- removing said temporary dielectric layer;
- forming a diffusion barrier on the sidewalls of said conductive base;
- forming an oxygen stable layer on the sidewalls of said diffusion barrier, wherein said diffusion barrier prevents said oxygen stable layer from reacting with said conductive base and prevents said conductive base from oxidizing;
- forming a HDC dielectric over the conductive base and oxygen stable layer;
- and
- forming an upper electrode over the HDC dielectric.
A method for forming a DRAM comprising the steps of:
- providing a semiconductor body processed through interlevel dielectric formation, including the formation of isolation structures, wordlines, bitlines contacts, and bitlines;
- depositing an etchstop layer over said interlevel dielectric;
- forming a temporary dielectric layer over said etchstop layer;
- forming a pattern over the temporary dielectric layer, said pattern exposing portions of the temporary dielectric layer over a plurality of storage node areas;
- etching said temporary dielectric layer and said etchstop layer using said pattern to remove said temporary dielectric layer and etchstop layer in said storage node areas;
- removing said pattern;
- forming a conductive base in each of said storage node areas;
- removing said temporary dielectric layer;
- forming a diffusion barrier on the sidewalls of said conductive bases;
- forming an oxygen stable layer on the sidewalls of said diffusion barrier, wherein said diffusion barrier prevents said oxygen stable layer from reacting with said conductive bases and prevents said conductive bases from oxidizing;
- forming a HDC dielectric over the conductive bases and oxygen stable layer;
- and
- forming an upper electrode over the HDC dielectric.
Dependencies are inferred from the claim text.