US 6,184,073 B2Granted

Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region

AssigneeMotorola, Inc.

InventorsCraig S. Lage, Mousumi Bhat, Yeong-Jyh Tom Lii, Andrew G. Nagy, Larry E. Frisa, Stanley M. Filipiak, David L. O'Meara, T. P. Ong, Michael P. Woo, Terry G. Sparks, Carol M. Gelatos

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Abstract

A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Claims14

Dependent claims

A process for forming a semiconductor device comprising the steps of:

forming a first conductive layer over a primary surface of a substrate;
forming a first insulating layer over the first conductive layer;
patterning the first conductive layer and the first insulating layer, wherein:
this step forms a first conductive member over a first portion of the substrate,
from a top view, the first conductive member has a shape;
and
from a top view, the first insulating layer has a shape that is substantially similar to the shape of the first conductive member;
forming a first doped region and a second doped region within the substrate near its primary surface, wherein from a top view, the first conductive member lies between the first doped region and the second doped region;
and
forming a first interconnect that electrically connects the first doped region to the second doped region, wherein the first interconnect:
extends over the first conductive member and the first insulating layer;
and
is electrically insulated from the first conductive member in a vertical direction by the first insulating layer.

10 more elements

A process for forming a semiconductor device comprising the steps of:

forming a first conductive region, a second conductive region, and third conductive region and a first insulating layer, wherein:
wherein from a top view, the second conductive region lies between the first and third conductive regions;
and
the second conductive region lies at an elevation higher than each of the first and third conductive regions;
and
the first insulating layer is patterned and overlies the second conductive region but does not overlie the first and third conductive regions;
forming a second insulating layer over the first, second, and third conductive regions, wherein:
the second insulating layer has a thickness of at least approximately 1000 angstroms and has a pre-patterned surface;
this step is performed after the first insulating layer has been patterned;
forming a patterned masking layer on the pre-patterned surface of the second insulating layer, wherein:
the patterned masking layer is a first patterned masking layer formed on the second insulating layer;
the patterned masking layer has a first masking layer opening that overlies the first, second and third conductive regions;
and
the pre-patterned surface of the second insulating layer is an only exposed surface of the second insulating layer within the first masking layer opening;
etching the second insulating layer to form a second insulating layer opening over the first, second, and third conductive regions, wherein the second insulating layer opening:
exposes portions of the first and third conductive regions, but not second conductive region;
and
the patterned masking layer is an only masking layer used to form the second insulating layer opening;
removing the patterned masking layer;
forming a conductive film over the second insulating layer and within the second insulating layer opening, wherein this step is performed after the step of etching the second insulating layer but before forming any other masking layers over the second insulating layer;
and
removing portions of the conductive film overlying the second insulating layer to form a first inlaid interconnect within the second insulating layer opening, wherein the first inlaid interconnect is electrically connected to the first and third conductive regions but is electrically insulated from the second conductive region by at least the first insulating layer.

19 more elements

Dependencies are inferred from the claim text.