US 6,184,071 B2Granted

Semiconductor device and method for fabricating the same

AssigneeHyundai Electronics Industries Co., Ltd.

InventorSeung Ho Lee

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Abstract

Semiconductor device and method for fabricating the same, which can improve an isolation characteristic and prevent a leakage current in conducting a borderless process, the device including a semiconductor substrate having an active region and a field region defined thereon, a bilayered gate electrode formed in one direction on the active region, a trench formed in the field region, an isolation region formed in, and on the trench to form a step to the semiconductor substrate so as to be projected from the semiconductor substrate, an insulating film barrier formed along a boundary of the active region projected from the semiconductor substrate, impurity regions in the semiconductor substrate in the active region on both sides of the gate line, a planar protection film having contact holes to the impurity regions on both sides of the active region, and a contact plug formed in each of the contact holes.

Claims16

Dependent claims

A method for fabricating a semiconductor device, comprising the steps of:

(1) defining an active region and a field region on a semiconductor substrate;
(2) depositing a first insulating film on the semiconductor substrate, and forming a second insulating film pattern on the field region;
(3) forming sidewall spacers at sides of the second insulating film pattern;
(4) removing the first insulating film to expose the semiconductor substrate in the active region, and forming a gate insulating film;
(5) forming a planar first conduction layer on the active region to a height identical to the second insulating film pattern;
(6) forming a third insulating film on the first conduction layer on the active region;
(7) removing the first insulating film and the second insulating film on the field region;
(8) forming a trench in the field region;
(9) forming a fourth insulating film in the trench;
(10) forming a buried insulating film on an entire surface of a resultant body;
(11) planarizing the buried insulating film, the fourth insulating film, the first conduction layer and the sidewall spacers, to leave the first conduction layer on the active region and the sidewall spacers at a boundary of the active region and the field region, and for the buried insulating film on the trench to form a step to the semiconductor substrate;
(12) forming a second conduction layer on an entire surface, and etching the first conduction layer and the second conduction layer to form the gate electrode on the active region;
(13) forming impurity regions in the active region on both sides of the gate electrode;
(14) forming a planar protection film to have contact holes to the impurity regions;
and,
(15) forming a contact plug in each of the contact holes.

13 more elements

A method for fabricating a semiconductor device, comprising the steps of:

(1) defining an active region and a field region on a semiconductor substrate;
(2) depositing a first insulating film on the semiconductor substrate, and forming a second insulating film pattern on the field region;
(3) forming sidewall spacers at sides of the second insulating film pattern;
(4) removing the first insulating film to expose the semiconductor substrate in the active region, and forming a gate insulating film;
(5) forming a planar first conduction layer on the active region to a height identical to the second insulating film pattern;
(6) forming a third insulating film on the first conduction layer on the active region;
(7) removing the first insulating film and the second insulating film on the field region;
(8) forming a trench in the field region;
(9) forming a fourth insulating film in the trench;
(10) forming a buried insulating film on an entire surface of a resultant body;
(11) planarizing to leave the buried insulating film, the first conduction layer and the sidewall spacers;
(12) planarizing the buried insulating film, the fourth insulating film, the first conduction layer and the sidewall spacers to leave the first conduction layer on the active region and the sidewall spacers at a boundary of the active region and the field region, and for the buried insulating film on the trench to form a step to the semiconductor substrate;
(13) removing the sidewall spacers at a periphery of the active region to form grooves, the grooves extending from the edge of the trench into the field region;
(14) filling the grooves to form insulating film barriers;
(15) forming a second conduction layer on an entire surface, and etching the first conduction layer and the second conduction layer to form the gate electrode on the active region;
(16) forming impurity regions in the active region on both sides of the gate electrode;
(17) forming a planar protection film to have contact holes to the impurity regions;
and,
(18) forming a contact plug in each of the contact holes.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/435,361Filed 8 Nov 1999
Priority: KR 99/167920 Jan 1999
Granted: 6 Feb 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10D 84/0149
The components including insulated gates, e.g. IGFETs: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
H10D 84/0151
The components including insulated gates, e.g. IGFETs: manufacturing their isolation regions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe