Memory device with multiple input/output connections
AssigneeMicron Technology, Inc.
InventorStephen L. Casper
Life of this patent
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Abstract
A memory device is described which is fabricated as an integrated circuit and uses distributed bond pads for electrical connection to an external conductive lead. The distributed bond pads are attached to a external lead, thereby eliminating bus lines on the integrated circuit memory. Distributed buffer circuits are described which can be included with the distributed bond pads to increase data communication time between the memory device and an external processor.
Claims10
A method of reducing data communication time in an integrated memory circuit, comprising:
- fabricating an integrated memory circuit on a semiconductor die having a plurality of memory subarray circuits coupled to a plurality of data communication bond pads distributed thereon, wherein the data communication bond pads are coupled to the subarrays by buffered input/output buffer circuits;
- providing a lead frame having an electrically conductive lead for bonding to the data communication bond pads;
- and
- bonding the data communication bond pads to the electrically conductive lead for bi-directional communication with an external processor.
A method of making an integrated circuit memory device, comprising:
- fabricating an integrated memory chip having a memory cell array with a plurality of subarrays;
- fabricating a plurality of data communication bond pads on the integrated memory chip, the data communication bond pads being coupled to the subarrays by buffered with input/output buffer circuits;
- forming an electrically conductive lead for coupling to the plurality of data communication bond pads;
- and
- electrically connecting the plurality of data communication bond pads to the conductive lead.
A method for providing bi-directional data communication between an integrated memory circuit and an external processor, comprising:
- fabricating a memory device as a semiconductor die having an array of memory cells arranged in a plurality of subarrays, the memory device having at least one electrically conductive lead;
- fabricating a plurality of data communication data communication bond pads on the memory device;
- electrically coupling the data communication bond pads to the at least one conductive lead so that a plurality of bond pads are connected electrically to the at least one conductive lead, wherein the data communication bond pads are coupled to the plurality of subarrays through a plurality of buffer circuits for data communication between the plurality of data communication bond pads and the plurality of subarrays.
A method of reducing data communication time in an integrated memory circuit, comprising:
- fabricating an integrated memory circuit on a semiconductor die having a plurality of memory subarray circuits coupled to a plurality of data communication bond pads distributed thereon, wherein the data communication bond pads are coupled to the subarrays by buffered input/output buffer circuits;
- providing a lead frame having an electrically conductive lead for bonding to certain of the data communication bond pads;
- and
- bonding at least two of the bond pads to the electrically conductive lead for bi-directional data communication between memory array circuits and an external processor.
A method of making an integrated circuit memory device, comprising:
- fabricating an integrated memory chip having a memory cell array with a plurality of subarrays;
- fabricating a plurality of data communication bond pads on the integrated memory chip, the bond pads being coupled to the subarrays by buffered with input/output buffer circuits;
- forming an electrically conductive lead for coupling to the plurality of data communication bond pads;
- and
- electrically connecting at least two of the plurality of data communication bond pads to the conductive lead.
A method for providing bi-directional data communication between an integrated memory circuit and an external processor, comprising:
- fabricating a memory device as a semiconductor die having an array of memory cells arranged in a plurality of subarrays, the memory device having at least one electrically conductive lead;
- fabricating a plurality of data communication bond pads on the memory device, wherein the data communication bond pads are coupled to the plurality of subarrays through a plurality of buffer circuits for data communication between the plurality of data communication bond pads and the plurality of subarrays;
- electrically coupling at least two of the data communication bond pads to the at least one conducive lead so that a plurality of bond pads are connected electrically to the at least one conductive lead.
A method of making an integrated circuit comprising:
- fabricating an integrated circuit die having a plurality of distributed data communication connections, wherein the data communication bond pads are buffered input/output buffer circuits;
- and
- electrically connecting at least two of the plurality of distributed data communication connections to a conductive lead of an external device for bi-directional data communication between the integrated circuit and the external device.
A method of interconnecting a plurality of memory subarrays of an integrated memory circuit, comprising:
- fabricating the an integrated memory circuit die from a plurality of sub array sections providing extended data communication leads from the subarray sections providing a plurality of data communication bond pads adjacent to the sub array sections, the bond pads coupled to the extended data communication leads, wherein the data communication bond pads are coupled to the plurality of subarray sections through a plurality of buffer circuits for data communication between the plurality of data communication bond pads and the plurality of subarray sections;
- providing a lead frame having at least one conductor;
- coupling at least two data communication bond pads to a lead frame conductor for providing data communication external to the memory circuit.
Dependencies are inferred from the claim text.