Method for fabricating semiconductor device
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsToyoji Chino, Takayuki Yoshida, Kenichi Matsuda
Life of this patent
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Abstract
A method for fabricating a semiconductor device, in which a semiconductor chip having a first surface and a second surface substantially parallel to each other is mounted on a submount such that the first surface faces the submount, includes: a first step of applying resin to at least one of the semiconductor chip and the submount; a second step of applying a pressure to the semiconductor chip and the submount so that the semiconductor chip and the submount are bonded to each other by the resin, resulting in electrical connection therebetween; and a third step of performing at least one of a film formation process, an etching process, a patterning process, and a washing process for the second surface of the semiconductor chip.
Claims2
A method for fabricating a semiconductor device in which a semiconductor chip having a first surface and a second surface substantially parallel to each other is mounted on a submount such that the first surface faces the submount comprising:
- a first step of forming a region of a metal having a low melting point on at least one of the first surface of the semiconductor chip and the submount;
- after the first step, a second step of heating the metal to a temperature close to the melting point thereof while applying a pressure to the semiconductor chip and the submount so that the semiconductor chip and the submount are bonded to each other by the metal, resulting in electrical connection therebetween;
- after the second step, a third step of performing at least one of a film formation process, an etching process, a patterning process, and a washing process for the second surface of the semiconductor chip,
- a fourth step of performing an oxide removal operation on the second surface;
- and
- after the fourth step, a fifth step of performing an atomic layer bonding of a further semiconductor chip onto the second surface of the semiconductor chip.
Dependencies are inferred from the claim text.