Microprocessor

A digital system comprising a microprocessor, wherein the microprocessor comprises:

• fetch circuitry for fetching a sequence of execution packets, wherein each execution packet comprises up to a first number of instructions;
• a first set of fimctional units connected to receive instructions from the fetch circuitry, the first set of functional units operable to execute a first plurality of instruction types;
• a second set of functional units connected to receive instructions from the fetch circuitry;
• wherein the second set of functional units is operable to execute the first plurality of instruction types;
• dispatch circuitry connected between the fetch circuitry and the first set of functional units and the second set of functional units, the dispatch circuitry operable to dispatch each instruction of each execution packet to both the first set of functional units and to the second set of functional units, such that all instructions of a given execution packet are executed in parallel, and
• wherein the dispatch circuitry selectively dispatches each instruction of each execution packet to either the first set of functional units or to the second set of functional units in response to a bit in each instruction.

A method of operating a digital system having a microprocessor, the method comprising the steps of:

• fetching a sequence of execution packets for execution by the microprocessor, wherein each execution packet contains up to N instructions that are executed in parallel by the microprocessor;
• dispatching all instructions of a first execution packet for parallel execution on plural sets of functional units in the microprocessor, wherein the plural sets of finctional units are virtually identical, wherein each instruction of each execution packet is selectively dispatched to either a first set of functional units or to a second set of functional units in response to a bit in each instruction;
• executing all instructions of the first execution packet in parallel on the plural sets of functional units;
• and
• repeating the steps of dispatching and executing for each execution packet of the sequence of execution packets, such that for each execution packet instructions of the same type can be dispatched to any and all of the plural sets of functional units, such that a first instruction of a first type from a given first execution packet is executed on the first set of the plural sets of finctional units while a second instruction of the first type from the given execution packet is executed in parallel on the second set of the plural sets of functional units.