Virtual register sets
AssigneeBrecis Communications
InventorDonald L. Sollars
Life of this patent
Estimating the term…
Abstract
One or more sets of one or more cache lines of cache locations of an apparatus, such as a processor, a system embedded with a processor, and the like, are dynamically operated at the same or different time periods as different register sets to supply source operands and to accept destination operands for instruction execution. The different register sets may be of the same or of different virtual register files, and if the different register sets are of different virtual register files, the different virtual register files may be of the same or of different architectures. The cache locations implementing the registers may be directly accessed using cache addresses or content addressed using memory addresses.
Claims17
An apparatus comprising:
- cache memory having first one or more cache lines of cache locations;
- and
- one or more control units coupled to said cache memory that dynamically operate said first one or more cache lines of cache locations during a first time period as registers of a first register set, and during a second time period as registers of a second register set;
- wherein said one or more control units include a mapping unit coupled to said cache memory that operates to map during said first time period a first operand register designator of a first instruction to a first cache address of a first of the first one or more cache lines of cache locations being dynamically operated as a first register of the first register set, and to map during the second time period a second operand register designator of a second instruction to the same first cache address of the same first cache location being dynamically operated as a second register of the second register set.
A method comprising:
- a) during a first time period, operating first one or more cache lines of cache locations as registers of a first register set to execute a first instruction;
- and
- b) during a second time period, operating the same first one or more cache lines of cache locations as registers of a second register set to execute a second instruction;
- wherein
- step (a) comprises mapping during said first time a first operand register designator of the first instruction to a first of the first one or more cache lines of cache locations being dynamically operated as a first register of the first register set, and
- step (b) comprises mapping during the second time period a second operand register designator of the second instruction to the same first of the first one or more cache lines of cache locations being dynamically operated as a second register of the second register set.
A method comprising:
- a) during a first time period, operating first one or more cache lines of cache locations as registers of a first register set to execute a first instruction:
- b) during a second time period, operating the same first one or more cache lines of cache locations as registers of a second register set to execute a second instruction;
- (c) during the first time period, performing a first arithmetic/logic operation specified by the first instruction, including at least either employment of a first source operand retrieved from a first of the first one or more cache lines of cache locations being dynamically operated as a first register of the first register set or providing a first designation operand for storage in said first cache location, and
- (d) during the second time period, performing a second arithmetic/logic operation specified by a second instruction, including at least either employment of a second source operand retrieved from the same first of the first one or more cache lines of cache locations being dynamically operated as a second register of the second register set, or providing a second destination operand for storage in the same first cache location.
Dependencies are inferred from the claim text.