Content addressable memory device
AssigneeFast-Chip, Inc.
InventorsAlex E. Henderson, Walter E. Croft
Life of this patent
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Abstract
A content addressable memory device is provided which may include a novel CAM cell structure which reduces the total power dissipated by the CAM and improves the match time for the CAM. The novel CAM cell structure may include a CMOS implemented compare cell and a wide AND gate which combines the match decisions for each CAM cell into a match decision. The CAM cell structure may be implemented in a variety of different CAM devices, including dual port CAM devices, CAM devices with individual bit masking, event co-processors and database co-processors.
Claims19
An apparatus for comparing at least one bit stored in a content addressable memory device against at least one compare bit, comprising:
- a first input for receiving the stored bit from the content addressable memory device,
- a second input for receiving the compare bit,
- a compare logic unit adapted to perform a compare between the compare bit and the stored bit and,
- an output which actively generates a match signal when the compare bit and the stored bit match and actively generates a non-match signal when the compare bit does not match the stored bit, for reducing power dissipation by eliminating pre-charge and pull-up functions.
A content addressable memory (CAM) cell for a high density CAM array of one or more CAM cells, comprising:
- a memory cell for storing a data bit comprising at least one input for receiving the data bit and at least one output for transmitting the data bit,
- a compare cell for comparing a compare bit with the data bit, the compare cell comprising an input coupled to receive the data bit from the memory cell, an input coupled to receive the compare bit, and an output for asserting a high signal when the compare bit matches the data bit, and asserting a low signal when the compare bit does not match the data bit, whereby power dissipation is reduced by eliminating pre-charge and pull-up functions and,
- at least one logic gate coupled to receive the output of the compare cell and capable of cooperating with other CAM cell logic gates to determine if one or more CAM cells contain matches.
A method for comparing at least one stored bit in a content addressable memory device against at least one compare bit comprising the steps of:
- reading the compare bit,
- reading the stored bit,
- comparing the compare bit against the stored data bit and,
- generating a compare signal based on the bit comparison wherein the compare signal is actively drawn high when the compare bit and stored bit match, and actively drawn low when the compare bit and stored bit do not match, and whereby the step of generating a compare signal reduces power dissipation by eliminating pre-charge and pull-up functions.
Dependencies are inferred from the claim text.