Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams

A method of testing a buffer memory device containing a multi-register cache memory array and a supplemental memory array therein, said method comprising the steps of:

• writing first data to at least one of a plurality of first addresses within a first register in the cache memory array;
• transferring the first data to at least one of a plurality of second addresses within a second register in the cache memory array;
• reading the first data from the second register in the cache memory array;
• and
• reading identifications of the first and second registers that are independent of the plurality of first and second addresses from the memory device.

A method of testing a buffer memory device containing a multi-register cache memory array and a supplemental memory array therein, said method comprising the steps of:

• writing first test data to a first register in the cache memory array;
• transferring the first test data from the first register to the supplemental memory array;
• transferring an identification of the first register to the supplemental memory array;
• transferring the first test data from the supplemental memory array to a second register in the cache memory array;
• reading the first test data from the second register;
• and
• reading an identification of the first register and an identification of the second register from the buffer memory device.

A method of testing a buffer memory device containing a multi-register cache memory array and a supplemental memory array therein, said method comprising the steps of:

• writing first test data to a first register in the cache memory array;
• transferring the first test data from the first register to the supplemental memory array;
• transferring the first test data from the supplemental memory array to a second register in the cache memory array;
• reading the first test data from the second register;
• and
• reading an identification of the first register and an identification of the second register from the buffer memory device;
• wherein said step of writing first test data to a first register comprises writing first test data and an identification of the first register to the first register.

A method of testing a memory device containing a plurality of multi-port registers and control logic that performs arbitration to determine which registers comprise multi-port write registers and which registers comprise multi-port read registers, said method comprising the steps of:

• arbitrating to determine a write register;
• writing first data to the write register;
• arbitrating to determine a read register;
• transferring the first data to the read register;
• reading the first data from the read register;
• and
• reading an identification of the write register from the memory device.

A method of testing a first-in first-out buffer memory device that is responsive to asynchronous read and write clock signals, comprising the steps of:

• writing first data into a first multi-port register in-sync with the write clock signal;
• writing second data into a second multi-port register in-sync with the write clock signal;
• transferring the first data from the first multi-port register into a supplemental memory array within the buffer memory device;
• then
• transferring the first data from the supplemental memory array into the second multi-port register;
• reading the first data from the second multi-port register in-sync with the read clock signal;
• and
• reading an identification of the first multi-port register from the memory device.

A method of testing a memory device having an embedded memory array therein, comprising the steps of:

• writing test data and an address of a first register into least one of a plurality of first addresses within the first register;
• transferring the test data and the address of the first register to the embedded memory array;
• writing test data, the address of the first register and an address of a second register into at least one of a plurality of second addresses within the second register;
• and
• reading the test data and the addresses of the first and second registers from the second register.