Method and apparatus for levelizing transfer delays for a channel of devices such as memory devices in a memory subsystem

A method comprising:

• determining a first delay value for a first memory device by iteratively increasing the first delay value from an initial delay value, the first delay value being a number of cycles delay until data is received by a controller from the selected memory device;
• determining a next delay value for a next memory device starting at the first delay value;
• selecting the greater of the first delay value and the next delay value as the controller delay value;
• testing whether the controller delay value is a maximum controller delay value;
• and
• if the controller delay value is the maximum controller delay value then:
• storing the maximum controller delay value as the controller delay value in a register of the controller;
• and
• stopping iterative testing to determine the controller delay value.

A method comprising:

• determining an individual memory delay value for each of a plurality of memory devices, the individual memory delay value being a number of delays up to a maximum delay value which levelizes a read delay for the plurality of memory devices;
• and
• testing whether a device delay value for a memory device is less than a maximum device delay value;
• if the device delay value is greater than the maximum device delay value then disabling the memory device by assigning an unused device identification number;
• if the device delay value is less than the maximum device delay value then testing whether another device delay value for another memory device is less than the maximum device delay value.

A system comprising:

• a processor;
• a memory controller coupled to the processor;
• a plurality of memory devices coupled to the memory controller;
• and
• a separate memory device having stored thereon a plurality of instructions which, if executed by the system, cause the system to perform a set of operations comprising:
• determining a controller delay value by iteratively testing memory transfers to determine a largest transfer latency value using a subset of a plurality of memory controller delays for at least one of a plurality of memory devices;
• and
• determining a memory device delay value for each of the plurality of memory devices by testing memory transfers using at least one delay value for each of the plurality of memory devices.

An article comprising a machine readable medium storing instructions that, if executed by a machine, cause the machine to perform a set of operations comprising:

• determining a first delay value for a first memory device by iteratively increasing the first delay value from an initial delay value, the first delay value being a number of cycles delay until data is received by a controller from the selected memory device;
• determining a next delay value for a next memory device starting at the first delay value;
• selecting the greater of the first delay value and the next delay value as the controller delay value;
• testing whether the controller delay value is a maximum controller delay value;
• and
• if the controller delay value is the maximum controller delay value then:
• storing the maximum controller delay value as the controller delay value in a register of the controller;
• and
• stopping iterative testing to determine the controller delay value.

An article comprising a machine readable medium storing instructions that, if executed by a machine, cause the machine to perform a set of operations comprising:

• determining an individual memory delay value for each of a plurality of memory devices, the individual memory delay value being a number of delays up to a maximum delay value which levelizes a read delay for the plurality of memory devices;
• and
• testing whether a device delay value for a memory device is less than a maximum device delay value;
• if the device delay value is greater than the maximum device delay value then disabling the memory device by assigning an unused device identification number;
• if the device delay value is less than the maximum device delay value then testing whether another device delay value for another memory device is less than the maximum device delay value.

A system comprising:

• a processor;
• a memory controller coupled to the processor;
• a plurality of memory devices coupled to the memory controller;
• and
• a separate memory device having stored thereon a plurality of instructions which, if executed by the system, cause the system to perform a set of operations comprising:
• determining a first delay value for a first memory device by iteratively increasing the first delay value from an initial delay value, the first delay value being a number of cycles delay until data is received by a controller from the selected memory device;
• determining a next delay value for a next memory device starting at the first delay value;
• selecting the greater of the first delay value and the next delay value as the controller delay value;
• testing whether the controller delay value is a maximum controller delay value;
• and
• if the controller delay value is the maximum controller delay value then:
• storing the maximum controller delay value as the controller delay value in a register of the memory controller;
• and
• stopping iterative testing to determine the controller delay value.

A system comprising:

• a processor;
• a memory controller coupled to the processor;
• a plurality of memory devices coupled to the memory controller;
• and
• a separate memory device having stored thereon a plurality of instructions which, if executed by the system, cause the system to perform a set of operations comprising:
• determining an individual memory delay value for each of a plurality of memory devices, the individual memory delay value being a number of delays up to a maximum delay value which levelizes a read delay for the plurality of memory devices;
• and
• testing whether a device delay value for a memory device is less than a maximum device delay value;
• if the device delay value is greater than the maximum device delay value then disabling the memory device by assigning an unused device identification number;
• if the device delay value is less than the maximum device delay value then testing whether another device delay value for another memory device is less than the maximum device delay value.