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US 6,172,545 B2Granted
Delay circuit on a semiconductor device
AssigneeNEC Corporation
InventorToshio Ishii
Life of this patent
Estimating the term…
Abstract
A delay circuit based on gate delay enables precise adjustment of a delay value. The delay circuit is composed of a plurality of p-channel transistors and n-channel transistors connected in series which are provided with capabilities that differ, ranging from the transistors closer to a power supply to the transistors closer to an output end so as to change the output drive capability and the input capacity independently, thereby improving the adjustment accuracy of the delay value of the circuit.
Claims6
A delay circuit on a semiconductor device, the delay circuit comprising:
- a plurality of p-channel transistors and a plurality of n-channel transistors connected in series from a high-potential power supply to a low-potential power supply;
- an input signal being commonly supplied to the gate terminals of said plurality of p-channel transistors and n-channel transistors;
- and
- the junction point of the p-channel transistor farthest from said high-potential power supply and the n-channel transistor farthest from said low-potential power supply providing an output terminal;
- wherein the current drive capabilities of said plurality of p-channel transistors and the current drive capabilities of said plurality of n-channel transistors are different, ranging from the transistors closer to said power supplies to the transistors closer to said output terminal;
- and
- wherein a ratio of said current drive capabilities of said p-channel transistors closer to said power supplies to said p-channel transistors closer to said output terminal is equal to a ratio of said current drive capabilities of said n-channel transistors closer to said power supplies to said n-channel transistors closer to said output terminal.
4 more elements
Dependencies are inferred from the claim text.