Method of making a metallized recess in a substrate

A method of forming a semiconductor testing device comprising:

• providing a substrate having an upper surface;
• forming a depression in said upper surface;
• forming a dielectric first layer upon said upper surface and extending continuously thereon within said depression;
• removing said dielectric first layer within said depression and from a portion of said upper surface adjacent to said depression by etching said dielectric first layer with an etch recipe that is more selective to said substrate than to said dielectric first layer;
• forming an electrically conductive film composed of a refractory metal upon said dielectric first layer and extending continuously upon said portion of the upper surface adjacent to said depression and within said depression;
• forming a masking layer upon said electrically conductive film;
• and
• selectively removing said electrically conductive film to form an electrical contact upon said dielectric first layer and extending continuously upon said upper surface of said depression.

A method of forming a semiconductor testing device comprising:

• forming a dielectric first layer upon an upper surface of a substrate;
• removing a portion of said dielectric first layer to expose said upper surface of said substrate;
• forming a spacer upon said upper surface and upon said dielectric first layer;
• forming a depression into said substrate adjacent said spacer;
• removing said spacer to expose a portion of said upper surface adjacent to said depression;
• and
• forming an electrically conductive film upon said dielectric first layer and extending continuously upon said portion of the upper surface adjacent to said depression and within said depression;
• forming a masking layer upon said electrically conductive film;
• and
• selectively removing said electrically conductive film to form an electrical contact upon said dielectric first layer and extending continuously upon a surface within the depression.

A method of forming a semiconductor testing device comprising:

• forming a dielectric first layer upon an upper surface of a substrate;
• removing a portion of said dielectric first layer to expose a first portion of said upper surface of said substrate;
• forming a spacer upon at least some of said first portion of said upper surface and upon said dielectric first layer;
• and
• removing said spacer and at least some of said first portion of said upper surface to form a depression in said substrate including:
• a ledge beneath said upper surface of said substrate;
• and
• a pit surface beneath said ledge and said upper surface of said substrates forming an electrically conductive film upon said upper surface of said substrate and extending continuously upon said ledge and within said depression upon said pit surface;
• forming a masking layer upon said electrically conductive film;
• and
• selectively removing said electrically conductive film to form an electrical contact upon said dielectric first layer and extending continuously upon said upper surface of said substrate.

A method of forming a semiconductor testing device comprising:

• forming a dielectric first layer upon an upper surface of a substrate;
• anisotropically etching said dielectric first layer with an etch recipe that is more selective to said substrate than to said dielectric first layer to expose a first 5 portion of said upper surface of said substrate;
• forming a spacer upon at least some of said first portion of said upper surface and upon said dielectric first layer;
• forming a depression in said substrate adjacent said spacer;
• removing said spacer and at least some of said first portion of said upper surface to form a depression in said substrate including:
• a planar ledge beneath said upper surface of said substrate;
• and
• a planar pit surface beneath said ledge and said upper surface of said substrate, the ledge and the pit surface being parallel to each other;
• anisotropically etching said substrate forming a Ti layer upon said upper surface;
• forming a TiN layer upon said Ti layer;
• and
• forming a W layer upon said TiN layer and extending continuously upon said ledge and said pit surface.

A method of forming a semiconductor testing device comprising:

• forming in succession, a plurality of dielectric layers on a substrate, the substrate having an upper surface, each subsequent dielectric layer having a composition different from the previous dielectric layers adjacent thereto;
• performing a first etching process through said plurality of dielectric layers to expose said upper surface of said substrate;
• performing a second etching process through said plurality of dielectric layers with an etch recipe that is more selective to some of said plurality of dielectric layers than to other of said plurality dielectric layers, wherein at least one of said first and second etching processes forms a depression in said substrate;
• and
• forming an electrically conductive film upon said upper surface and extending continuously upon said plurality of said dielectric layers to a surface within said depression;
• forming a masking layer upon said electrically conductive film;
• and
• selectively removing said electrically conductive film to form an electrical contact upon said plurality of dielectric layers and extending continuously upon said surface within said depression.

A method of forming a semiconductor testing device comprising:

• providing a substrate having an upper surface;
• forming a dielectric first layer on the upper surface of the substrate;
• forming a dielectric second layer on the dielectric first layer;
• selectively removing said dielectric first layer and said dielectric second layer to expose at least a portion of said upper surface of said substrate;
• forming a depression in said substrate adjacent to the at least a portion of said upper surface of the substrate, said depression having a top surface;
• etching the dielectric first layer and the dielectric second layer with an etch recipe that is more selective to the dielectric first layer that to the dielectric second layer;
• forming a metal layer upon the dielectric second layer and extending continuously upon the dielectric first layer and upon the at least a portion of said upper surface of the substrate, and upon the top surface of the depression,
• forming a masking layer upon said metal layer;
• and
• selectively removing said metal layer to form an electrical contact upon said dielectric first and second layers and extending continuously upon the top surface of the depression.

A method of forming a semiconductor testing device comprising:

• providing a semiconductor substrate having an upper surface;
• forming a plurality of dielectric layers sequentially upon the semiconductor substrate, each dielectric layer having a composition different from the dielectric layers adjacent thereto;
• performing a first etching process through said plurality of dielectric layers to expose at least a portion of said upper surface of said semiconductor substrate;
• performing a second etching process upon the semiconductor substrate to form a depression therein extending beneath the upper surface of the semiconductor substrate, wherein there is a breach in each dielectric layer of said plurality of dielectric layers, each said breach having a width, wherein the width of the dielectric layer adjacent to said upper surface of the semiconductor substrate is less than the width of the other of said breaches and wherein the width of each breach is greater than the width of the breach that is adjacent thereto and that is closer to said substrate;
• and
• forming a conductive layer extending continuously upon:
• each dielectric layer of said plurality of dielectric layers;
• the exposed portion of the upper surface of the semiconductor substrate;
• and
• the depression in the semiconductor substrate, forming a masking layer upon said conductive layer;
• and
• selectively removing said conductive layer to form an electrical contact upon said plurality of dielectric layers and extending continuously upon the depression in the semiconductor substrate.