Method of making a high-voltage transistor with multiple lateral conduction layers

A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

• (a) forming a well region of a first conductivity type in a substrate of a second conductivity type, the well region having a laterally extended portion;
• (b) implanting a first dopant of the second conductivity type into the laterally extended portion of the well region to form a first buried region therein;
• (c) implanting a second dopant of the second conductivity type into the laterally extended portion of the well region to form a second buried region therein, the second buried region being disposed at a different depth in the well region than the first buried region such that a JFET conduction channel is formed between the first and second buried regions;
• and
• (d) forming a drain diffusion region of the first conductivity type in the well.

A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

• (a) forming a well region of a first conductivity type in a substrate of a second conductivity type, the well region having a laterally extended portion with a lateral boundary;
• (b) implanting a dopant of the second conductivity type into the substrate to form a first buried region within the laterally extended portion of the well region and a second buried region in the substrate, the first buried region being disposed beneath a surface of the substrate such that dual JFET conduction channels are formed above and below the first buried region;
• (c) forming a gate insulated from the substrate by a gate oxide layer, the gate extending over the substrate adjacent the well region;
• (d) implanting a dopant of the first conductivity type into the substrate to form a source diffusion region spaced-apart from the well region and above the second buried region, the dopant also being implanted into the well region to form a drain diffusion region spaced-apart from the first buried region, a channel region being formed between the source diffusion region and the well region under the gate;
• and
• (e) forming source and drain electrodes connected to the source and drain diffusion regions, respectively.

A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

• (a) forming a well region of a first conductivity type in a substrate of a second conductivity type, the well region having a laterally extended portion with a lateral boundary;
• (b) successively implanting a dopant of the second conductivity type into the substrate to form a plurality of buried layers within the laterally extended portion of the well region, each successive implant being performed at a different energy such that the plurality of buried layers are spaced-apart from one another thereby creating an associated plurality of JFET conduction channels within the well region;
• (c) forming a gate insulated from the substrate by a gate oxide layer, the gate extending over the substrate adjacent the well region;
• (d) forming a source diffusion region in the substrate spaced-apart from the well region, a channel region being formed between the source diffusion region and the well region under the gate;
• and
• (e) forming a drain diffusion region in the well region.

A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

• (a) forming a well region of a first conductivity type in a substrate of a second conductivity type, the well region having a laterally extended portion;
• (b) forming a masking layer over the laterally extended portion of the well region, the masking layer having a varying thickness;
• and
• (c) implanting a dopant of the second conductivity type through the masking layer to form a buried region within the well region, the buried region comprising separate buried sections disposed at different depths within the well region corresponding to the varying thickness of the masking layer.

A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

• forming an epitaxial layer of a first conductivity type over a substrate of a second conductivity type;
• forming a first region of the second conductivity type in the epitaxial layer, the first region having a boundary;
• forming an insulated gate over a portion of the first region;
• forming a source diffusion region in the first region a channel region being defined in an area of the first region between the source diffusion region and the boundary, the insulated gate being disposed over the channel region;
• implanting a dopant into the epitaxial layer to form a buried region of the second conductivity type disposed therein, the buried region being disposed beneath a top surface of the epitaxial layer such that dual JFET conduction channels are formed above and below the buried region;
• and
• forming a drain diffusion region in the epitaxial layer spaced-apart from the buried region.