Method and apparatus for manifold array processing
AssigneeBillions of Operations Per Second, Inc.
InventorsGerald G. Pechanek, Nikos P. Pitsianis, Edwin F. Barry, Thomas L. Drabenstott
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Abstract
A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.
Claims34
An interconnection system for a plurality of processing elements (PEs) connected in an N.times.M array where N and M are both greater than one, each PE having a communications port for transmitting and receiving data and commands, the PEs grouped into clusters, and the interconnection system comprising:
- inter-PE connection paths, and
- a cluster switch connected to said PEs so as to combine mutually exclusive inter-PE connection paths between clusters and to thereby substantially reduce the number of communication paths required to provide inter-PE connectivity equivalent to that of conventional torus-connected PE arrays, said cluster switch further comprising connections to provide direct communications between transpose PEs and between hypercube complement PEs, wherein data and commands may be transmitted and received at said communications ports in one of eight selected modes:
- a) transmit east/receive west mode for transmitting data to an east PE via the communications port while receiving data from a west PE via the communications port,
- b) transmit north/receive south mode for transmitting data to a north PE via the communications port while receiving data from a south PE via the communications port,
- c) transmit south/receive north mode for transmitting data to a south PE via the communications port while receiving data from a north PE via the communications port,
- d) transmit west/receive east mode for transmitting data to a west PE via the communications port while receiving data from an east PE via the communications port,
- e) transpose transmit/receive mode for transmitting and receiving between transpose PEs, and hypercube transmit/receive mode for transmitting and receiving between distance 1 hypercube PEs,
- f) hypercube transmit/receive modes for transmitting and receiving between select distance 2 hypercube PEs, and,
- g) hypercube complement transmit/receive mode for transmitting and receiving between distance d,d-dimensional hypercube complement PEs.
A parallel processor, comprising:
- N clusters of M processing elements, each processing element having a communications port through which the processing element transmits and receives data over a total of B wires,
- communications paths which are less than or equal to (M) (B) wires wide connected between pairs of said clusters, each cluster member in the pair containing processing elements which are torus nearest neighbors to processing elements in the other cluster of the pair, each path permitting communications between said cluster pairs in two mutually exclusive torus directions, that is, South and East or South and West or North and East or North and West,and
- multiplexers connected to combine 2 (M) (B)-wire wide communications between said cluster pairs into said less than or equal to (M) (B)-wires wide paths.
A parallel processor, comprising:
- N clusters of M processing elements, each processing element having a communications port through which the processing element transmits and receives data over a total of B wires and each processing element within a cluster being formed in a closer physical proximity to the other processing elements within a cluster than to processing elements outside the cluster,
- communications paths which are less than or equal to (M) (B)-wires wide connected between pairs of said clusters, each cluster member in the pair containing processing elements which are hypercube nearest neighbors to processing elements in the other cluster of the pair, each path permitting communications between said cluster pairs in two mutually exclusive torus directions, that is, South and East or South and West or North and East or North and West, or between two hypercube dimensions, and multiplexers connected to combine 2 (M) (B) wires wide communications between said cluster pairs into said less than or equal to (M) (B) wires wide paths.
A parallel processor comprising a plurality of processing elements (PEs) arranged in clusters;
- inter-PE communication paths connecting said PEs such that pairs of PEs communicate in a single step on available communication paths within clusters and between a first PE in one cluster and a second PE in one of two clusters adjacent to the cluster containing said first PE, wherein all PEs in a cluster are completely connected, and wherein said PEs have separate send and receive ports and communication between any PE in a first cluster and any PE in an adjacent second cluster can be done simultaneously for all PEs in said first and second clusters.
Dependencies are inferred from the claim text.