US 6,167,492 A · Circuit and method for maintaining order of memory access requests initiated by devices coupled to a multiprocessor system

Abstract

A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions. The first and second non-coherent memory access transactions include first and second memory addresses, respectively. The first and second non-coherent memory access transactions further include first and second pipe identifications, respectively. The node circuit maps the first and second memory addresses to first and second node numbers, respectively. The first and second pipe identifications are compared. If the first and second pipe identifications compare equally, then the first and second node numbers are compared. First and second coherent memory access transactions are generated by the node coupled to the I/O bridge wherein the first and second coherent memory access transactions correspond to the first and second non-coherent memory access transactions, respectively. The first coherent memory access transaction is transmitted to one of the nodes of the multiprocessor computer system. However, the second coherent memory access transaction is not transmitted unless the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

Claims18

Dependent claims

A method of operating a multiprocessor computer system comprising a plurality of circuit nodes and a plurality of memories, wherein each circuit node comprises at least one microprocessor coupled to a memory controller, wherein each memory controller is coupled to one of the plurality of memories, wherein the plurality of circuit nodes are in data communication with each other, wherein each circuit node is uniquely identified by a node number, wherein one of the circuit nodes is coupled to an I/O bridge, wherein the I/O bridge is configured to generate and transmit a non-coherent memory access transaction, wherein the one of the circuit nodes is configured to receive the non-coherent memory access transaction, wherein the one of the circuit nodes is configured to transform the non-coherent memory access transaction into a coherent memory access transaction, and wherein each non-coherent memory access transaction comprises at least one command packet containing a pipe identification and a memory address, the method comprising:

generating a first non-coherent memory access transaction, wherein the first non-coherent memory access transaction comprises a first memory address and a first pipe identification;
generating a second non-coherent memory access transaction after generating the first non-coherent memory access transaction, wherein the second non-coherent memory access transaction comprises a second memory address and a second pipe identification;
mapping the first and second memory addresses to first and second node numbers, respectively;
comparing the first and second pipe identifications;
comparing the first and second node numbers if the first and second pipe identifications compare equally;
generating a first coherent memory access transaction corresponding to the first non-coherent memory access transaction;
generating a second coherent memory access transaction corresponding to the second non-coherent memory access transaction if the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

4 more elements

A method of operating a multiprocessor computer system comprising a plurality of circuit nodes and a plurality of memories, wherein each circuit node comprises at least one microprocessor coupled to a memory controller, wherein each memory controller is coupled to one of the plurality of memories, wherein adjacent circuit nodes are connected via a coherent link, wherein each circuit node is assigned a unique node number, wherein one of the circuit nodes is coupled to an I/O bridge via a non-coherent link, wherein the I/O bridge is configured to generate and transmit a non-coherent memory access packet via the non-coherent link to the one of the circuit nodes, wherein the one of the circuit nodes is configured to transform the non-coherent memory access packet into a coherent memory access packet, wherein the one of the circuit nodes is configured to transmit the coherent memory access packets to another of the circuit nodes, wherein the non-coherent memory access packet comprises a pipe identification and a memory address, and wherein the coherent memory access packet comprises one of the node numbers and the memory address, the method comprising:

generating a first non-coherent memory access packet, wherein the first non-coherent memory access packet comprises a first memory address and a first pipe identification;
generating a second non-coherent memory access packet after generating the first non-coherent memory access packet, wherein the second non-coherent memory access packet comprises a second memory address and a second pipe identification;
mapping the first and second memory addresses to first and second node numbers, respectively;
comparing the first and second pipe identifications;
comparing the first and second node numbers if the first and second pipe identifications compare equally;
generating a first coherent memory access packet corresponding to the first non-coherent memory access packet;
generating a second coherent memory access packet corresponding to the second non-coherent memory access packet;
transmitting the first coherent memory access packet, and;
transmitting the second coherent memory access packet if the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

6 more elements

A multiprocessor computer system comprising:

a plurality of node circuits each one of which comprises at least one microprocessor in data communication with a memory controller, wherein each node circuit is uniquely identified by a node number, and wherein the plurality of node circuits are in data communication with each other;
a plurality of memories each one of which is in data communication with one of the memory controllers;
an input/output (I/O) bridge circuit in data communication with a first node circuit, wherein the I/O bridge circuit is configured to sequentially generate first and second non-coherent command packets, wherein the first non-coherent command packet contains a first pipe identification and a first memory address, and wherein the second non-coherent command packet contains a second pipe identification and a second memory address;
wherein the first node circuit is configured to receive the first and second non-coherent command packets, wherein the first node circuit further includes a memory circuit for mapping the first and second memory addresses of the received first and non-coherent second command packets to first and second node numbers, respectively, wherein the first node circuit comprises a node number compare circuit for comparing the first and second node numbers, and wherein the first node circuit comprises a pipe identification compare circuit for comparing the first and second pipe identifications;
wherein the first node circuit is configured to generate first and second coherent command packets corresponding to the received first and second non-coherent command packets, wherein the first node circuit is configured to transmit the first coherent command packet, and wherein the first node circuit is configured to transmit the second coherent command packet if the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

2 more elements

A multiprocessor computer system comprising:

a plurality of node circuits each one of which comprises at least one microprocessor in data communication with a memory controller, wherein each node circuit is uniquely identified by a node number;
a plurality of memories each one of which is in data communication with one of the memory controllers;
a plurality of coherent links for transmitting coherent memory access transactions between node circuits, wherein each coherent link connects a pair of node circuits;
an input/output (I/O) bridge circuit;
a non-coherent link for transmitting non-coherent memory access transactions between the I/O bridge and a first node circuit, wherein the I/O bridge circuit is configured to sequentially generate first and second non-coherent memory access transactions, wherein the first non-coherent memory access transaction contains a first pipe identification and a first memory address, and wherein the second non-coherent memory access transaction contains a second pipe identification and a second memory address;
wherein the first node circuit is configured to receive the first and second non-coherent memory access transactions, wherein the first node circuit further includes a first memory circuit for mapping the first and second memory addresses of the received first and non-coherent second memory access transactions to first and second node numbers, respectively, wherein the first node circuit comprises a node number compare circuit for comparing the first and second node numbers, and wherein the first node circuit comprises a pipe identification compare circuit for comparing the first and second pipe identifications;
wherein the first node circuit is configured to generate a first coherent memory access transaction corresponding to the received first non-coherent memory access transaction, and wherein the first node circuit is configured to generate a second coherent memory access transaction corresponding to the received second non-coherent memory access transaction if the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

4 more elements

Dependencies are inferred from the claim text.

Circuit and method for maintaining order of memory access requests initiated by devices coupled to a multiprocessor system

Life of this patent

Circuit and method for maintaining order of memory access requests initiated by devices coupled to a multiprocessor system

Life of this patent

Abstract

Claims18