Dual microprocessor electronic trip unit for a circuit interrupter

Abstract

An electronic trip unit having two microprocessors one of which monitors the load voltage and current within the normal operating range and performs the metering and delayed trip algorithms associated with that range. A second microprocessor monitors the load current for excursions outside the normal operating range and processes those algorithms and functions associated with the instantaneous and overcurrent trip protection modes of the trip unit. Each microprocessor receives inputs representative of the monitored current that are scaled to a different factor corresponding to the range the microprocessors are assigned to monitor. In one embodiment the electronic trip unit is controlled by a master controller and in turn controls a number of accessory devices, wherein one of the microprocessors is a slave to the master controller network and the other microprocessor is a master to the accessory slave network. The microprocessors communicate with each other and either one can trip the circuit on detection of a fault condition.

Dependencies are inferred from the claim text.