Transistor with low resistance tip and method of fabrication in a CMOS process

A method of forming a pair of complementary metal oxide semiconductor transistors in a semiconductor substrate, said method comprising the steps of:

• a) forming a first gate dielectric and a first gate electrode on a first portion of said semiconductor substrate having a p-type conductivity and forming a second gate dielectric and a second gate electrode on a second portion of said semiconductor substrate having a n-type conductivity;
• b) forming a boron doped glass layer over said second portion of said semiconductor substrate and said second gate electrode;
• c) forming a silicon nitride layer over said first portion of said semiconductor substrate including said first gate electrode and over said boron doped glass layer over said second portion of said semiconductor substrate including said second gate electrode;
• d) removing said silicon nitride layer and said boron doped glass layer from said second portion of said silicon substrate and from the top of said second gate electrode to thereby form a first pair of composite sidewall spacers adjacent to opposite sides of said second gate electrode;
• and
• e) forming a semiconductor material on said second portion of said semiconductor substrate adjacent to said first pair of composite sidewall spacer.

A method of forming a pair of complementary metal oxide semiconductor transistors in a semiconductor substrate, said method comprising the steps of:

• a) forming a first gate dielectric and a first gate electrode on a first portion of a first surface of said semiconductor substrate having a first conductivity type and forming a second gate dielectric and a second gate electrode on a second portion of said first surface of said semiconductor substrate having a second conductivity type;
• b) forming a first pair of silicon nitride spacers along opposite sidewalls of said first gate electrode and a first pair of silicon nitride spacers along opposites sidewalls of said second gate electrode;
• c) forming a pair of recesses in said first portion of said semiconductor substrate in alignment with said first pair of silicon nitride spacers along said first gate electrode and a pair of recesses in said second portion of said semiconductor substrate in alignment with said first pair of silicon nitride spacers along said second gate electrode;
• d) forming a first masking layer over said second portion of said semiconductor substrate and said second gate electrode, and while said second portion of said semiconductor substrate and said second gate electrode is masked, forming a first semiconductor material having said second conductivity type in said pair of recesses formed in said first portion of said semiconductor substrate;
• e) forming a second masking layer over said first portion of said semiconductor substrate and said first gate electrode and while said first portion of said semiconductor substrate and said first gate electrode are masked, forming a second semiconductor material having said first conductivity type in said pair of recesses formed in said second portion of said semiconductor substrate.

A method of forming a pair of complementary metal oxide semiconductor transistors in a semiconductor substrate, said method comprising the steps of:

• a) forming a first gate dielectric and a first gate electrode on a first portion of said semiconductor substrate having a p-type conductivity and forming a second gate dielectric and a second gate electrode on a second portion of said semiconductor substrate having a n-type conductivity;
• b) forming a boron doped glass layer over said second portion of said semiconductor substrate and said second gate electrode;
• c) forming a silicon nitride layer over said first portion of said semiconductor substrate including said first gate electrode and over said boron doped glass layer over said second portion of said semiconductor substrate including said second gate electrode;
• d) removing said silicon nitride layer from said first portion of said semiconductor substrate so as to form a first pair of silicon nitride spacers adjacent to opposite sides of said first gate electrode, and removing said silicon nitride layer and said boron doped glass layer from said second portion of said silicon substrate and from the top of said second gate electrode to thereby form a first pair of composite sidewall spacers adjacent to opposite sides of said second gate electrode;
• e) forming a pair of recesses in said first portion of said semiconductor substrate adjacent to said first pair of silicon nitride spacers and a pair of recesses in said second portion of said semiconductor substrate in alignment with said composite sidewall spacers;
• f) forming an undoped semiconductor material in said pair of recess in said first portion of said semiconductor substrate and in said pair of recesses in said second portion of said semiconductor substrate;
• g) implanting ions of n-type conductivity into said undoped semiconductor material formed in said pair of recess on said first portion of said semiconductor substrate to thereby form n-type semiconductor material;
• and
• h) implanting ions of p-type conductivity into said semiconductor material formed in said pair of recesses in said second portion of said semiconductor substrate to thereby form p-type semiconductor material.

A method of forming a pair of complementary metal oxide semiconductor transistors in a semiconductor substrate, said method comprising the steps of:

• a) forming a first gate dielectric and a first gate electrode on a first portion of a first surface of said semiconductor substrate having a first conductivity type and forming a second gate dielectric and a second gate electrode on a second portion of said first surface of said semiconductor substrate having a second conductivity type;
• b) forming a silicon nitride layer over said first portion of said semiconductor substrate including said first gate electrode and over said second portion of said semiconductor substrate including said second gate electrode;
• c) removing said silicon nitride layer from said second portion of said silicon substrate and from the top of said second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of said second gate electrode;
• d) depositing a semiconductor material on said second portion of said first surface of said semiconductor substrate adjacent to said first pair of silicon nitride spacers;
• and
• e) diffusing dopants from said deposited semiconductor material into said substrate beneath said first pair of sidewall spacers.

A method of diffusing impurities in a semiconductor process, said method comprising the steps of:

• providing a semiconductor substrate having a plurality of regions doped with impurities;
• annealing said substrate in a first ambient comprising oxygen and nitrogen at a first temperature for a first period of time;
• and
• after annealing in said first ambient, annealing said substrate in a second ambient comprising nitrogen at a second temperature for a second period of time, wherein said first anneal and said second anneal occur insitu.

A method of forming a CMOS integrated circuit, said method comprising the steps of:

• forming a gate dielectric layer on a semiconductor substrate;
• forming a first gate electrode and a second gate electrode on said gate dielectric layer;
• placing ions of a first conductivity type in alignment with opposite sidewalls of said first gate electrode;
• placing ions of a second conductivity type in alignment with opposite sidewalls of said second gate electrode;
• and
• utilizing only a single Rapid Thermal Process to drive and activate said first conductivity type ions and said second conductivity type ions into said substrate to form a first pair of source/drain regions adjacent to said first gate electrode and a first pair of source/drain regions adjacent to said second gate electrode wherein said rapid thermal process utilizes a first ambient comprising oxygen and nitrogen and a second ambient comprising nitrogen.