Silicon carbide semiconductor device and method of manufacturing the same

A method of manufacturing a silicon carbide semiconductor device including an n type surface channel layer in which a current flows when a voltage is applied to a gate electrode, the method comprising steps of:

• preparing a p type semiconductor layer;
• forming the n type surface channel layer on the p type semiconductor layer, and first and second n type semiconductor regions on both sides of the n type surface channel layer so that the first and second n type semiconductor regions are connected to each other through the n type surface channel layer;
• forming a gate insulation film on the n type surface channel layer by thermal oxidation;
• performing a high temperature annealing treatment at a temperature equal to or higher than 1200.degree. C.;
• and
• forming the gate electrode on the n type surface channel layer through the gate insulation film.

A method of manufacturing a silicon carbide semiconductor device including an n type silicon carbide semiconductor layer with a channel region in which a channel is induced when a voltage is applied to a gate electrode, the method comprising steps of:

• forming first and second p type semiconductor regions on both sides of the channel region;
• forming a gate insulation film on the channel region of the n type silicon carbide semiconductor layer by thermal oxidation;
• performing a high temperature annealing treatment at a temperature equal to or higher than 1200.degree. C.;
• and
• forming the gate electrode on the n type silicon carbide semiconductor layer through the gate insulation film.

A method of manufacturing a silicon carbide semiconductor substrate, comprising steps of:

• forming an n type semiconductor layer from silicon carbide on a main surface of an n type silicon carbide semiconductor substrate to have a resistance larger than that of the n type silicon carbide semiconductor substrate;
• forming a p type base region in a specific surface portion of the n type semiconductor layer with a first depth;
• forming an n type surface channel layer on the n type semiconductor layer and on the p type base region;
• forming an n type source region in a specific surface portion of the p type base region with a second depth shallower than the first depth of the p type base region;
• forming a gate insulation film on the n type surface channel layer by thermally oxidizing a surface portion of the n type surface channel layer at a first temperature;
• performing a reoxidation annealing in an oxidation ambience at a second temperature lower than the first temperature;
• performing an annealing at an oxidation rate smaller than that in the reoxidation annealing;
• forming a gate electrode on the gate insulation film;
• forming a source electrode to contact the n type source region and the p type base region;
• and
• forming a drain electrode on a back surface of the n type semiconductor substrate opposite the main surface.