Bus bridge and method for ordering read and write operations in a write posting system

A method for ordering write operations relative to read operations between first and second buses joined by a bus bridge, the write operations being mastered from the first bus and destined to the second bus and the read operations being mastered from the second bus and destined for completion on the second bus by way of a coherent cache in the bus bridge, comprising the steps of:

• (a) providing write posting storage for queueing the write operations from the first bus;
• (b) counting a number of write operations received in said write posting storage;
• (c) counting a number of write operations completed on the second bus;
• (d) measuring an age of data held in a cache line in the coherent cache in units of write operations received in said write posting storage since said data in said cache line was fetched;
• and
• (e) delaying completion of said read operations when said age of said data to be read from the coherent cache is less than a difference between said number of write operations received in said write posting storage and said number of write operations completed on the second bus.

A bus bridge for ordering write operations mastered from a first bus and destined to a second bus relative to read operations mastered from the second bus and destined for completion on the second bus by way of a coherent cache in said bus bridge, said bus bridge comprising:

• write posting storage for queueing the write operations from the first bus;
• a producer write counter for counting a number of write operations received in said write posting storage;
• a consumer write counter for counting a number of write operations completed on the second bus;
• a cache line ager counter for measuring an age of data held in a cache line in the coherent cache in units of write operations received in said write posting storage since said data in said cache line was fetched;
• and
• ordering logic for delaying completion of said read operations when said age of said data to be read from the coherent cache is less than a difference between said number of write operations received in said write posting storage and said number of write operations completed on the second bus.