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US 6,157,331 AGranted
Sigma delta modulator with automatic saturation detection and recovery
AssigneeTritech Microelectronics, Ltd.
InventorsLiusheng Liu, David Ho Seng Poh
Life of this patent
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Abstract
In the present invention is described a forward feed sigma delta modulator of higher order having automatic saturation detection and recovery. The modulator is separated into two parts which are connected together when there is no saturation, and disconnected when saturation is detected and recovery takes place. The first part contains an integrator and input output circuitry to allow continuous operation of the modulator. The second part contains additional integrators to provider for a higher order modulator and the saturation detector. The modulator can be constructed of single ended or differential switched capacitor technology, and there is a digital saturation detection scheme.
Claims23
A sigma delta modulator circuit, comprising:
- a) an input circuit containing a first integrator circuit forming a first order sigma delta modulator and connected to produce a quantized output from an analog input signal,
- b) a set of serially connected integrator circuits connected to said input circuit and further connected to a saturation detector circuit,
- c) said first integrator circuit forming a high order sigma delta modulator in conjunction with said set of serially connected integrator circuits when saturation is not detected by said saturation detector,
- d) said set of serially connected integrator circuits disconnected from said input circuit by said saturation detector circuit when saturation is detected, leaving said first order sigma delta modulator operating between said analog input and said quantized output.
1 more element
A continuously operating sigma delta modulator circuit, comprising:
- a) a first circuit part comprising an input circuit connected to a first integrator circuit, a quantizer connected to output of said first integrator circuit through a parameter circuit summing junction, and a DAC feeding back output of said quantizer to input of said first integrator circuit,
- b) a second circuit part comprising several integrator circuits connected in series from a second integrator circuit to a last integrator circuit with outputs of each integrator circuit connected through parameter circuits to a summing junction and a saturation detector monitoring an output of one of said several integrator circuits,
- c) output of said saturation detector controlling switches connecting said second circuit part to said first circuit part,
- d) an input to said second circuit part connected to said first circuit part when saturation is not detected by said saturation detector,
- e) said input to said second circuit part disconnected from said first circuit and controlled to recover from saturation when a saturation signal is detected by said saturation detector,
- f) said second circuit part reconnected to said first circuit part when said saturation signal is not detected by said saturation detector.
3 more elements
A modulator circuit, comprising:
- a) a series connected forward feed sigma delta modulator,
- b) several integrator circuits connected in series with an output of a first integrator circuit connected to an input of a second integrator circuit and continuing to an output of a next to last integrator circuit connected to an input of a last integrator circuit,
- c) parameter circuits connected to outputs of said several integrator circuits with outputs of said parameter circuits summed together in an output summing junction and connected to input of a quantizer circuit,
- d) said output summing junction connected to an input summing junction of said first integrator circuit through a first feedback switch,
- e) output of said quantizer circuit producing a digital output of said sigma delta modulator and connected to a one bit DAC,
- f) output of said DAC fed back through a second feedback switch to said input summing junction of said first integrator circuit,
- g) analog input to said sigma delta modulator connected through a first input switch to said input summing junction,
- h) a second input switch connecting circuit ground to said input summing junction,
- i) a saturation detector connected to output of one of said several integrator circuits connected in series to said first integrator circuit,
- j) output of said saturation detector controlling said first and second input switches and said first and second feedback switches.
7 more elements
A method of detecting sigma delta modulator saturation and recovery, comprising:
- a) monitoring an output voltage of an integrator circuit subsequent to a first integrator circuit for voltage saturation,
- b) disconnecting a second integrator circuit through a last integrator circuits from said first integrator circuit,
- c) feeding back outputs of parameter circuits connected to said second through last integrator circuits to an input summation circuit of said second integrator circuit,
- d) connecting circuit ground to input summation circuit of said second integrator circuit,
- e) waiting a predetermined amount of time for circuitry to recover from saturation and restoring circuits to original connections,
- f) retuning to step (a) and monitoring said output voltage of said integrator circuit subsequent to said first integrator circuit for voltage saturation.
3 more elements
A method for detecting sigma delta modulator saturation and recovery using digital techniques, comprising:
- a) monitoring a one bit output of a switched capacitor coupled sigma delta modulator,
- b) detecting a predetermined number of consecutive logic signals of a same value and turning on a saturation signal,
- c) disconnecting a second integrator circuit through last integrator circuits from a first integrator circuit,
- d) feeding back output sum of parameter circuits connected to said second through last integrator circuits to an input summation circuit of said second integrator circuit,
- e) connecting circuit ground to input summation circuit of said second integrator circuit,
- f) waiting a predetermined number of clock cycles for circuitry to recover from saturation, turning off saturation signal and restoring circuits to original connections,
- f) returning to step (a) and monitoring said one bit output of said switched capacitor coupled sigma delta modulator.
4 more elements
Dependencies are inferred from the claim text.