Layout designing method and layout designing apparatus

A hierarchical layout designing apparatus comprising:

• means for arranging hard macro blocks and a soft macro block;
• means for forming a wiring which connects the hard macro blocks to each other using a path which passes above the soft macro block;
• evaluation means for evaluating an extent of an influence which a wiring passing above the soft macro block will exert on an internal wiring of the soft macro block;
• and
• formation means for forming the cell rows in the soft macro block after determining an extending direction in which the cell rows are to extend in the soft macro block, based on an extent of influence determined by the evaluation means.

A computer readable recording medium in which a program has been recorded, said program controlling a computer to execute a process for hierarchical layout design of a semiconductor device, the process comprising:

• determining layout positions in which hard macro blocks and a soft macro block are to be placed;
• forming a wiring which connects the hard macro blocks to each other using a path which passes above the soft macro block;
• evaluation of an influence which the wiring passing above the soft macro block will exert on an internal wiring of the soft macro block;
• and
• determining a direction in which the cell rows are to extend in the soft macro block based on a result of the evaluation.