US 6,154,865 A · Instruction processing pattern generator controlling an integrated circuit tester

Abstract

A pattern generator for an integrated circuit tester includes an instruction memory storing addressable instructions (INST) and reading out each instruction when addressed by an address (ADDR) supplied as input thereto. An instruction processor receives each instruction read out of the instruction memory and alters the address input to the instruction memory in accordance with the received instruction so that the instruction memory reads out a next instruction. The instruction processor, which includes a conventional return address stack, is capable of executing conventional address increment, call and return instructions. The instruction processor is also capable of executing a temporary return instruction (TEMP) by incrementing its current address output to produce a new return address, by setting its address output to the value of a return address previously saved in the stack, by popping the saved return address from the stack, and by pushing the new return address onto the stack. Temporary return instructions enable instruction program flow to pass back and forth between a main program and a called subroutine.

Claims20

Dependent claims

An instruction processor (20) for responding to each input instruction of a sequence of input instructions by changing a value of an output address (ADDR), the instruction processor comprising:

stack means (32) for saving a return address when signaled to do so by an input PUSH signal and for discarding a saved return address when signaled to do so by an input POP signal, and
processing means (24, 26, 29, 30) for responding to at least one of said instructions (TEMP) by changing said output address from a current value to a value of a return address previously saved by said stack means, by generating a new return address, by signaling said stack means via said POP signal to discard the previously saved return address, and by signaling said stack means via said PUSH signal to save said new return address.

A pattern generator (23) comprising:

an instruction memory (22) for storing a plurality of addressable instructions (INST) and for reading out each instruction when addressed by an address (ADDR) supplied as input thereto, each instruction referencing a method of supplying a next address input to said instruction memory;
a vector memory (18) also addressed by said address (ADDR) supplied as input to said instruction memory, for storing a plurality of addressable vectors and for reading out each vector when addressed;
stack means (32) for saving a return addresses when signaled to do so by an input PUSH signal and for discarding a saved return address when signaled to do so by an input POP signal;
and
processing means (24, 26, 29, 30) for responding to each input instruction read out of said instruction memory by changing a current value of said address (ADDR), wherein said processing means responds to at least one of said instructions (TEMP) by changing said output address from a current value to a value of a return address previously saved by said stack means, by generating a new return address, by signaling said stack means via said POP signal to discard the previously saved return address, and by signaling said stack means via said PUSH signal to save said new return address.

2 more elements

An integrated circuit (IC) tester (10) comprising:

an instruction memory (22) for storing a plurality of addressable instructions (INST) and for reading out each instruction when addressed by an address (ADDR) supplied as input thereto, each instruction referencing a method of supplying a next address input to said instruction memory;
a vector memory (18) also addressed by said address (ADDR) supplied as input to said instruction memory, for storing a plurality of addressable vectors and for reading out each vector when addressed;
a tester channel (14) for receiving each vector read out of said vector memory and carrying out a test activity referenced by said vector;
stack means (32) for saving a return addresses when signaled to do so by an input PUSH signal and for discarding a saved return address when signaled to do so by an input POP signal;
and
processing means (24, 26, 29, 30) for responding to each input instruction read out of said instruction memory by changing a current value of said address (ADDR), wherein said processing means responds to at least one of said instructions (TEMP) by changing said output address from a current value to a value of a return address previously saved by said stack means, by generating a new return address, by signaling said stack means via said POP signal to discard the previously saved return address, and by signaling said stack means via said PUSH signal to save said new return address.

3 more elements

Dependencies are inferred from the claim text.

Instruction processing pattern generator controlling an integrated circuit tester

Life of this patent

Instruction processing pattern generator controlling an integrated circuit tester

Life of this patent

Abstract

Claims20