Read only memory embedded in a dynamic random access memory
AssigneeMicron Technology, Inc.
InventorTodd A. Merritt
Life of this patent
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Abstract
The present invention is embodied in a method and apparatus which provides a ROM embedded in an DRAM utilizing unused portions of the DRAM. By hardwiring the unused digitlines of the DRAM to either a specified voltage or ground, the outputs of the sense amplifiers associated with those unused digitlines can be programmed to output a specific logic state. By combining the outputs from several sense amplifiers, a fixed bit pattern can be produced. The fixed bit pattern can be used, for example, to generate a test data pattern for a Built-in Self Test or to generate an initialization sequence.
Claims55
A method of programming memory space of at least one DRAM memory array to function as a ROM memory area, said at least one DRAM memory array comprising a plurality of DRAM cells and a plurality of wordlines and digitlines for addressing said plurality of DRAM cells, said method comprising the steps of:
- selectively connecting at least one of said plurality of digitlines to one of two voltage sources, each of said voltage sources having a value which corresponds to a respective logical state used in said at least one DRAM memory array, to thereby form at least one programmed ROM memory area;
- reading a voltage value from said at least one digitline;
- and
- outputting a signal representing said voltage value read from said at least one digitline.
A method for generating a fixed bit pattern utilizing memory space of at least one DRAM memory array, said at least one DRAM memory array comprising a plurality of DRAM cells and a plurality of wordlines and digitlines for addressing said plurality of DRAM cells, said method comprising the steps of:
- selectively connecting at least one of said plurality of digitlines to one of two voltage sources, each of said voltage sources having a value which corresponds to a respective logical state used in said at least one DRAM memory array;
- reading a voltage value from said at least one digitline;
- and
- outputting a signal representing said voltage value read from said at least one digitline,
- wherein a plurality of said signals output are combined to produce said fixed bit pattern.
A semiconductor circuit comprising:
- a memory device, said memory device comprising at least one DRAM memory array, said at least one DRAM memory array comprising a plurality of DRAM cells, and a plurality of wordlines and digitlines for accessing said plurality of DRAM cells, each of said digitlines being associated with at least one of said DRAM cells;
- and
- a plurality of sense amplifiers for reading a voltage on a digitline when said digitline is activated,
- wherein at least one of said digitlines of said at least one DRAM memory arrays is connected to one of two voltage sources, each of said voltage sources having a value which corresponds to a respective logical state used in said DRAM memory array, to thereby function as a ROM storage area.
An integrated circuit comprising:
- a semiconductor circuit, said semiconductor circuit comprising a memory device, said memory device comprising at least one DRAM memory array, said at least one DRAM memory array comprising a plurality of DRAM cells and a plurality of wordlines and digitlines for accessing said cells, each of said digitlines being associated with at least one of said DRAM cells, and a plurality of sense amplifiers for reading a voltage on a digitline when said digitline is activated;
- and
- logic circuitry for performing functions beyond those required for operation of said DRAM memory array,
- wherein at least one of said digitlines of said at least one DRAM memory arrays is selectively connectable to one of two voltage sources, each of said voltage sources having a value which corresponds to a respective logical state used in said at least one DRAM memory array, to thereby function as a ROM storage area.
A processor system comprising:
- a central processing unit;
- and
- a semiconductor circuit, said semiconductor circuit comprising a memory device, said memory device comprising at least one DRAM memory array, said at least one DRAM memory array comprising a plurality of DRAM cells and a plurality of wordlines and digitlines for accessing said cells, each of said digitlines being associated with at least one of said DRAM cells, and a plurality of sense amplifiers for reading a voltage on a digitline when said digitline is activated,
- wherein at least one said digitlines of said at least one DRAM memory arrays is connected to one of two voltage sources, each of said voltage sources having a value which corresponds to a respective logical state used in said at least one DRAM memory array, to thereby function as a ROM storage area.
Dependencies are inferred from the claim text.