Method and apparatus for built-in self-test of smart memories

A self-testing smart memory, comprising:

• a data RAM;
• a data path, connected to said data RAM, wherein said data path includes a plurality of processing elements operable to perform specific functions;
• a broadcast RAM connected to said data path;
• memory test circuitry, coupled to said broadcast RAM and said data RAM, for testing said broadcast RAM and said data RAM, wherein said memory test circuitry includes:
• a first stimulus generator for generating and writing a pattern to said data RAM and said broadcast RAM;
• a first response analyzer for comparing the contents of said data RAM and said broadcast RAM with said pattern;
• data path test circuitry, coupled to said data path, for testing said specific functions of said plurality of processing elements of said data path wherein said data path test circuitry includes:
• a second stimulus generator for generating and transmitting a second pattern to said data path;
• said data path operable to process said second pattern and to generate processed data in response to said second pattern;
• and a response analyzer coupled to said data path and responsive to said processed data for analyzing said processed data;
• and
• a test controller for controlling said memory test circuitry and for controlling said data path test circuitry during testing.