High-speed test system for a memory device

A circuit device comprising:

• a plurality of circuit cells operable to store data therein during a write operation wherein the plurality of circuit cells include first and second sub-arrays of circuit cells;
• a plurality of output terminals, including first and second output terminals coupled to the first and second sub-arrays, respectively;
• a control circuit coupled to the first and second sub-arrays and being operable to transfer data from the first and second sub-arrays to the first and second output terminals, respectively, during a read operation;
• a test circuit coupled to the control circuit and the first and second sub-arrays, the test circuit, in response to a predetermined signal, testing data written to the first sub-array and outputting a test signal based on the testing;
• and
• a switch coupled to the test circuit and one of the plurality of output terminals, the switch receiving the predetermined signal from the control circuit and coupling the test circuit to the one output terminal in response thereto, and otherwise providing a direct output path for at least one of the first and second sub-arrays.

A semiconductor memory device comprising:

• a plurality of memory cells operable to store data therein during a write operation, the plurality of memory cells including first and second sets of sub-arrays of memory cells, each set having eight sub-arrays corresponding to a data word;
• a control circuit coupled to the plurality of memory cells and being operable to write data to, and read data from, the plurality of memory cells;
• a direct output path coupled between at least one of the first and second sub-arrays and an output terminal and constructed for testing a speed of the memory device during testing;
• and
• a test circuit having first and second compare circuits, the first compare circuit comparing bits in a first data word written to the first set of sub-arrays to each other and outputting a pass value for a test signal if all of the bits in the first data word match, and the second compare circuit comparing bits in a second data word written to the second set of sub-arrays to each other and to at least one bit from the first data word and outputting a pass value for the test signal if all of the bits of the second data word and the one bit from the first data word match.

A method of testing a semiconductor memory device having an array of memory cells and at least one output terminal, the method comprising:

• entering into a test mode;
• writing data to at least one memory cell of the array;
• testing the data written to the memory cell;
• providing a test signal indicating the results of the testing;
• selectively providing the test signal to a first output terminal when the memory device is in the test mode;
• and
• directly reading the data from the memory cell and providing the data to a second output terminal during speed testing of the memory device.