Debug interface including state machines for timing synchronization and communication

A debug interface for interfacing a processor to a debug device, the debug interface comprising:

• a serial input/output port;
• a trace logic coupled to the serial input/output port;
• and
• an interface logic coupled to the serial input/output port and coupled to the trace logic, the interface logic including a state machine for communicating commands and data among the serial input/output port, the trace logic, and the processor,
• the state machine starting and stopping a trace mode of operation upon receipt of commands from the external device so that the trace mode of operation is controlled without setting a break point or executing processor instructions that start and stop the trace mode;
• a decoder coupled to the interface logic and wherein the state machine reads commands and data from the serial input/output port and the trace logic, and wherein the decoder decodes commands read from the serial input/output port and the trace logic;
• and
• wherein the state machine has a plurality of states including,
• a command state for receiving written commands from the debug device;
• a decode state for passing the written commands to the decoder;
• and
• a wait state for waiting until a command communication is complete.

A debug interface for interfacing a processor core to a debug device, the debug interface comprising:

• a debug register;
• an input/output port coupled to the debug register and executing at an input/output port clock rate;
• a trace logic coupled to the debug register and executing at a trace logic clock rate;
• a processor interface state machine coupled to the debug register and connectable to the processor core, the processor interface state machine executing at a processor clock rate;
• and
• a debug port state machine coupled to the debug register and the processor interface state machine, and connectable to the debug device, the debug port state machine and the processor interface state machine generating timing signals to the debug register that are synchronized to the processor clock rate.

A debug interface for interfacing a processor core to a debug device, the debug interface comprising:

• a debug register;
• an input/output port coupled to the debug register and executing at an input/output port clock rate;
• a trace logic coupled to the debug register and executing at a trace logic clock rate;
• a processor interface state machine coupled to the debug register and connectable to the processor core, the processor interface state machine executing at a processor clock rate;
• and
• a debug port state machine coupled to the debug register and the processor interface state machine, and connectable to the debug device, the debug port state machine and the processor interface state machine generating handshake signals to communicate with the input/output port, the processor core, and the trace logic.

A debug interface for interfacing a processor core to a debug device, the debug interface comprising:

• a debug register;
• an input/output port coupled to the debug register and executing at an input/output port clock rate;
• a trace logic coupled to the debug register and executing at a trace logic clock rate;
• a processor interface state machine coupled to the debug register and connectable to the processor core, the processor interface state machine executing at a processor clock rate;
• and
• a debug port state machine coupled to the debug register and the processor interface state machine, and connectable to the debug device;
• and
• a decoder coupled to the debug register, the decoder for decoding commands from the input/output port and the trace logic.

A method of operating a processor during a trace operation that supplies trace records indicative of instruction execution flow in the processor, the method comprising:

• providing a debug interface state machine;
• selecting a trace entry point address that designates an instruction program counter value in an instruction memory of the processor;
• executing instructions in the processor at program counter locations determined by a program flow;
• comparing the program counter locations to the selected trace entry point address;
• when the program counter location is the same as the trace entry point address, generating an interrupt through an operation of the debug interface state machine;
• and
• executing an interrupt service routine including a trace mode program code.