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US 6,154,851 AGranted
Memory repair
AssigneeMicron Technology, Inc.
InventorsJoseph C. Sher, Gerg A. Blodgett
Life of this patent
Estimating the term…
Abstract
Method for repair of a memory array. In particular, a key is provided to inquire a memory array for ascertaining availability of redundant elements and programming a memory for access to such redundant elements. Alternatively, a second test key may be supplied to the memory for programming. In this manner, repair of the memory is effected. The memory may be a single memory integrated circuit (chip) or a memory module located in a system, such as a computer. Such repair may be done locally or remotely without uninstalling the defective memory.
Claims40
A system comprising:
- a memory device having a matrix of cells and having signal inputs;
- and
- a memory controller in electrical communication with the memory device, the memory controller to provide a sequence of control signals, including RAS and CAS signals, to the signal inputs, the sequence of control signals to condition the memory device to receive a key, the memory device in response to the key put into a mode to repair a defective one of said matrix of cells.
A memory controller comprising:
- a storage device to store information;
- and
- logic circuitry configured to initiate a write-column-address-strobe-before-row-address-strobe (WCBR) cycle in response to the information stored.
A memory repair system comprising:
- a first computer system comprising:
- a processing unit;
- a memory controller in electrical communication with the processing unit;
- a memory in electrical communication through RAS, CAS, address, and data signals with the memory controller, the memory including an array of memory cells;
- and
- an input/output device in electrical communication with the processing unit;
- a communication transport in communication with the first system through the input/output device;
- and
- a second computer system programmed to repair the memory of the first system, the second computer system in communication with the first computer system through the communication transport.
6 more elements
An apparatus comprising:
- a programmed computer having a memory controller and a memory device, the memory device having a matrix of memory cells, the programmed computer including programming to repair the memory while installed in the computer;
- the programmed computer operable in response to the programming to condition the memory controller to initiate a reserved cycle, to provide a key to the memory device, without adding a control line, to put the memory device into a mode with the key, to read from the memory device existence of at least one available redundant element, to provide an address to the memory device relating to a defective cell, and to program the memory device for accessing the redundant element.
An apparatus comprising:
- a programmed computer having a memory controller and a memory device, the memory device having a matrix of memory cells, the programmed computer including programming to repair the memory while installed in the computer;
- the programmed computer operable in response to the programming to condition the memory controller to initiate at least one column-address-strobe-before-row-address-strobe (CBR) cycle, to provide a key to the memory device, to put the memory device into a mode with the key, and to identify a defective cell of the memory device.
A system comprising:
- a programmed computer having a memory controller and a memory device, the memory device having a matrix of memory cells, the programmed computer including programming to repair the memory while installed in the computer;
- the programmed computer operable in response to the programming to condition the memory controller to initiate at least one reserved cycle, to provide at least one key to the memory device, to put the memory device into at least one mode with the key, to identify any defective cell of the memory cells, to read from the memory device existence availability of at least one redundant element, to provide at least one address to the memory device relating to the defective cell, and to program the memory device for accessing the redundant element to replace the defective cell.
A method for repair of a memory device having at least one defective memory cell in an array of memory cells, the method comprising:
- providing a reserved cycle to the memory device by transitioning in sequence a WE signal, a CAS signal, and a RAS signal;
- providing at least one key to the memory device while in the reserved cycle;
- putting the memory device into at least one mode with the key;
- identifying the defective memory cell;
- reading from the memory device existence of at least one available redundant element;
- providing an address to the memory device relating to the defective memory cell;
- and
- programming the memory device for accessing the redundant element instead of the defective memory cell.
5 more elements
A method of repairing a portion of a memory having matrix of memory elements, the matrix comprising a defective element and a redundant element, the method comprising:
- providing a sequence of signals including a RAS signal and a CAS signal to the memory;
- invoking a reserved cycle of the memory;
- providing a code key to the memory;
- invoking a inquiry mode using the code key;
- identifying a location associated with the defective element;
- and
- determining availability of the redundant element.
4 more elements
An apparatus comprising:
- a programmed computer comprising:
- a memory including programming and at least one memory device, the memory device having a matrix of cells and having signal inputs;
- and
- a memory controller including a RAS signal and a CAS signal in electrical communication through the RAS signal and the CAS signal with the memory device, the memory controller to provide a sequence of control signals to the signal inputs in response to the programming, the sequence of control signals to condition the memory device to receive a key, the key to put the memory device into a mode for repairing a defective one of said matrix of cells.
1 more element
A method for repairing a memory module while installed in a computer, the memory module having a plurality of memory chips each having an array of memory elements, the method comprising:
- providing a reserved sequence of control signals including RAS and CAS signals to the memory module;
- initiating a memory test of the memory module while installed in the computer;
- identifying a defective cell of said memory elements;
- locating which memory chip of said memory chips includes the defective cell;
- initiating a test mode for the memory chip while installed in the computer;
- determining availability of a redundant element of said memory elements;
- and
- programming the memory chip to access the redundant element instead of the defective cell.
5 more elements
A method for repair of a memory while installed in a computer, the memory having an array of cells, the method for repairing one or more bit errors in the array, the method comprising:
- providing a reserved cycle to the memory while installed in the computer;
- providing a first test key to the memory while installed in the computer;
- activating a test mode in response to the first test key;
- determining locations of one or more defective cells;
- ascertaining availability of one or more spare cells;
- activating a program mode in response to a second test key;
- providing a location associated with one or more of the defective cells;
- and
- using the location to program the memory.
6 more elements
A memory controller comprising:
- a register to store information;
- and
- logic circuitry configured to initiate a write-column-address-strobe-before-row-address-strobe (WCBR) cycle in response to the information stored.
A memory controller comprising:
- a decoder to store information;
- and
- logic circuitry configured to initiate a write-column-address-strobe-before-row-address-strobe (WCBR) cycle in response to the information stored.
Dependencies are inferred from the claim text.