Power failure safe computer architecture
AssigneeIntel Corporation
InventorsAlper Ilkbahar, Christopher Cheng
Life of this patent
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Abstract
A component powered by a first power supply activates a driving signal. The driving signal indicates that both a second power supply voltage has a magnitude greater than a reference voltage and an enable signal is active. A driver transfers the output signal when the driving signal is active. In a multi-processor computer system implementation, each of two processor cores are independently supplied power by each of two core power supplies while a single I/O power supply supplies power to the I/O rings of both processors. Each processor includes a bus isolation circuit to prevent its respective processor from loading the system bus in the event that a core power supply fails.
Claims22
A circuit to transfer an output signal comprising:
- a component to be powered by a first power supply, the component to activate a driving signal that indicates that both a second power supply voltage has a magnitude greater than a reference voltage and an enable signal is active;
- and
- a driver to transfer the output signal when the driving signal is active.
A processor comprising:
- a core coupled to a core power supply input port;
- a driver coupled to an I/O power supply input port, the driver having an input coupled to the core, an output coupled to an I/O port, and a control input;
- and
- a logic gate having an output coupled to the control input of the driver, the logic gate to output a driving signal that indicates that the core power supply is operational.
A processor comprising:
- a core coupled to a core power supply input port;
- and
- a bus isolation circuit coupled to an I/O power supply input port, the circuit preventing the processor from loading an external bus if a core power supply fails.
A computer system comprising:
- a first core power supply coupled to a first processor;
- a second core power supply coupled to a second processor, the second processor being coupled to the first processor via a system bus;
- an I/O power supply coupled to both the first and second processors;
- a first bus isolation circuit coupled to the I/O power supply, the first bus isolation circuit preventing the first processor from loading the system bus when the first core power supply fails;
- and
- a second bus isolation circuit coupled to the I/O power supply, the second bus isolation circuit preventing the second processor from loading the system bus when the second core power supply fails.
Dependencies are inferred from the claim text.