System for recovering from a concurrent branch target buffer read with a write allocation by invalidating and then reinstating the instruction pointer

A branch instruction prediction mechanism comprising:

• front-end circuitry that fetches and places an instruction within a pipeline and transmits a first instruction pointer associated with the instruction for branch prediction;
• back-end circuitry that writes information into a branch target buffer (BTB) cache;
• and
• a branch target buffer (BTB) circuit coupled to the front-end circuitry and the back-end circuitry, the BTB circuit including the branch target buffer (BTB) cache, in response to a BTB hardware conflict the BTB circuit enabling a write allocation to be performed by the back-end circuitry instead of the branch prediction by the front-end circuitry by (i) invalidating at least the first instruction pointer associated with a suppressed cache read to allow the write allocation to proceed, and (ii) recovering the first instruction pointer by reloading the first instruction pointer into the pipeline.

A method comprising:

• performing a write allocation to a branch target buffer (BTB) circuit;
• performing with a cache read to the BTB circuit concurrently with the write allocation;
• invalidating at least one instruction pointer placed within a pipeline of the BTB circuit, the at least one instruction pointer including a first instruction pointer associated with the cache read which is suppressed to allow the write allocation to proceed;
• and
• recovering the first instruction pointer by reloading the first instruction pointer into the BTB pipeline.

A method comprising:

• detecting a write allocation to a port of a branch target buffer (BTB) cache concurrent with a read to the port of the BTB cache;
• invalidating at least one instruction pointer placed within a BTB pipeline, the at least one instruction pointer including a first instruction pointer associated with the BTB cache read suppressed in favor of the write allocation;
• and
• recovering the first instruction pointer by reloading the first instruction pointer into the BTB pipeline.