Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values

A device, comprising:

• a plurality of arithmetic logic units configured to operate in parallel;
• a first register partitioned into a plurality of first slots;
• a second register partitioned into a plurality of second slots;
• and
• a decode unit configured to specify operands and operations for said plurality of arithmetic logic units, wherein the decode unit is configured to decode in one instruction:
• a first operand location for a first operand to be routed to a first one of said arithmetic logic units;
• a second operand location for a second operand to be routed to a second one of said arithmetic logic units;
• a third operand location for a third operand to be routed to said first one of said arithmetic logic units to be combined with said first operand according to a first operation;
• a fourth operand location for a fourth operand to be routed to said second one of said arithmetic logic units to be combined with said second operand according to a second operation;
• said first operation to be executed by said first arithmetic logic unit on said first operand;
• and
• said second operation to be executed by said second arithmetic logic unit on said second operand;
• wherein said first and second operand locations are determined by specifying said first register in said one instruction, whereby said first and second operand locations correspond to fixed ones of said first slots;
• and
• wherein said third and fourth operand locations are determined by specifying, in said one instruction, said second register and one of said second slots for said third operand and one of said second slots for said fourth operand, wherein said third and fourth operand locations are specified from any of said second slots.

A device, comprising:

• one or more first registers each partitioned into a first plurality of slots;
• one or more second registers each partitioned into a second plurality of slots;
• a plurality of arithmetic logic units configured to operate in parallel;
• and
• a decode unit configured to decode an instruction to specify operands and operations for said plurality of arithmetic logic units, wherein the instruction comprises:
• at least one router slot selection field for specifying for each arithmetic logic unit one of a plurality of operand locations from which an operand is to be routed, wherein said operand locations include said first plurality of slots from one of said first registers;
• a first operation code for specifying a first operation to be performed by at least a first one of said arithmetic logic units on the corresponding operand specified by said at least one router slot selection field and on an operand from a first fixed one of said second plurality of slots from one of said second registers, wherein said first fixed one of said second plurality of slots corresponds to said first one of said arithmetic logic units;
• and
• a second operation code for specifying a second operation to be performed by at least a second one of said arithmetic logic units on the corresponding operand specified by said at least one router slot selection field and on an operand from a second fixed one of said second plurality of slots from one of said second registers, wherein said second fixed one of said second plurality of slots corresponds to said second one of said arithmetic logic units.

A method for performing multiple operations within a single instruction cycle, comprising:

• decoding a single instruction specifying a first operation, a second operation, a first plurality of operand locations, and a second plurality of operand locations;
• dispatching a first plurality of operands from said first plurality of operand locations;
• dispatching a second plurality of operands from said second plurality of operand locations;
• wherein said first plurality of operands are dispatched from fixed operand slot locations in a specified first register, and wherein said second plurality of operands are dispatch from any specified slot of a specified second register;
• and
• performing said first operation upon one or more first pairs of operands, wherein each said first pair of operands comprises an operand from said first plurality of operands and an operand from said second plurality of operands, while performing said second operation upon one or more second pairs of operands, wherein each said second pair of operands comprises an operand from said first plurality of operands and an operand from said second plurality of operands.

A device, comprising:

• a first register partitioned into a first plurality of slots;
• an instruction decode unit for decoding an instruction to specify operands and operations to be performed on the operands, wherein the instruction comprises:
• a first encoded field of bits within said instruction for encoding a first operand and a second operand, wherein said first operand is selected from any one of said first plurality of slots or one of a set of specific values and wherein said second operand is selected from any one of said first plurality of slots or one of said set of specific values;
• a second encoded field of bits within said instruction for encoding a third operand and a fourth operand, wherein said third operand is selected from any one of said first plurality of slots or one of said set of specific values and wherein said fourth operand is selected from any one of said first plurality of slots or one of said set of specific values, wherein the number of bits for said second encoded field is less than the number of bits required to encoded said third and said fourth operands separately;
• a third encoded field of bits within said instruction for specifying a first operation to be performed on one or more of the operands specified by said first and second encoded fields of bits;
• and
• a fourth encoded field of bits within said instruction for specifying a second operation to be performed on one or more of the operands specified by said first and second encoded fields of bits.