Method and apparatus for employing a cycle bit parallel executing instructions

An apparatus comprising:

• a compiler for generating an executable file including compound instructions of varying length, each compound instruction including at least one operational instruction, each operational instruction including a corresponding cycle bit that indicates which of a set of multiple operational instructions can be logically executed simultaneously, wherein a number of operational instructions in a maximum length compound instruction is greater than a number of processors in a multi-processor system that are available to execute at least part of a compound instruction in parallel;
• an instruction register including a predetermined number of operational instruction storage slots for storing a predetermined number of operational instructions and corresponding cycle bits;
• an instruction fetching unit that, during a fetch cycle, fetches the operational instructions of compound instructions in the executable file and transfers the operational instructions and the corresponding cycle bits to storage slots of the instruction register;
• an instruction executing unit including multiple processors that, during an execute cycle, simultaneously execute all or part of a compound instruction in the instruction register in parallel depending on a state of the corresponding cycle bits, each processor executing an operational instruction in a corresponding operational instruction storage slot of the instruction register, any part of a compound instruction not fetched and executed during a current processing cycle being fetched and executed on one or more subsequent cycles;
• and
• whereby the executable file can be executed on a plurality of hardware platforms, each hardware platform having a potentially different hardware resource capacity for simultaneously executing operational instructions stored in its respective instruction register.

An apparatus comprising:

• a compiler for generating an executable file including compound instructions of varying length, each compound instruction including at least one operational instruction and corresponding cycle bit that indicates which of a set of multiple operational instructions can be logically executed simultaneously, wherein a number of operational instructions in a maximum length compound instruction can be greater than a number of processors in a multi-processor system that are to execute at least part of a compound instruction in a given execution cycle;
• an instruction register for storing a predetermined number of operational instructions, the predetermined number of operational instructions being less than the number of operational instructions in a maximum length compound instruction, each operational instruction having a corresponding cycle bit that indicates which of the predetermined number of operational instructions can be executed simultaneously;
• an instruction fetching unit that fetches the variable length compound instructions from the executable file and stores fetched operational instructions in the instruction register, the instruction fetching unit, at times, fetching part of a compound instruction;
• and
• an instruction executing unit including multiple digital processors for simultaneously executing a previously fetched set of operational instructions in the instruction register, any non-executed portion of a partially executed compound instruction being executed on subsequent fetch and execute cycles such that instruction executing units having fewer digital processors than a number of operational instructions in the maximum length compound instruction are capable of executing the same executable file.

In a multiprocessor system for simultaneously executing operational instructions of an executable file, an apparatus comprising:

• an instruction fetching unit that, during a fetch cycle, fetches the operational instructions from the executable file, the executable file including compound instructions of varying length, each compound instruction including a number of operational instructions that can be executed simultaneously, the executable file including at least one compound instruction having more operational instructions than available processors to execute such instructions simultaneously, the instruction fetching unit fetching part of a compound instruction when a compound instruction includes more operational instructions than available processors to simultaneously execute fetched operational instruction, any operational instructions of a partially fetched compound instruction not fetched on a current fetch cycle being fetched on one or more subsequent fetch cycles;
• and
• an instruction executing unit including multiple processors that, after a fetch cycle, simultaneously execute operational instructions fetched from the executable file, any subsequently fetched operational instructions of a partially fetched and executed compound instruction being executed on one or more subsequent processing cycles such that the executable file can be properly executed by instruction executing units having fewer processors than a number of operational instructions in a maximum length compound instruction.

A method comprising the steps of:

• generating an executable file including compound instructions of varying length, at least one compound instruction including multiple operational instructions, each operational instruction including a corresponding cycle bit indicating which of a set of multiple operational instructions can be logically executed simultaneously, wherein a number of operational instructions in a maximum length compound instruction can be greater than a number of processors in a multi-processor system that are available to execute at least part of a compound instruction in parallel;
• storing a predetermined number of operational instructions and corresponding cycle bits in a predetermined number of operational instruction storage slots of an instruction register;
• fetching the operational instructions of compound instructions in the executable file and transferring the operational instructions and corresponding cycle bits to storage slots of the instruction register;
• simultaneously executing all or part of a compound instruction in the instruction register in parallel depending on a state of the corresponding cycle bits, each processor executing an operational instruction in a corresponding operational instruction storage slot of the instruction register, any part of a compound instruction not fetched and executed during a current processing cycle being fetched and executed on one or more subsequent cycles;
• and
• whereby the executable file can be executed on a plurality of hardware platforms, each hardware platform having a potentially different numbers of executing units operating in parallel for simultaneously executing operational instructions in its respective instruction register.