Method and apparatus for addressing a memory resource comprising memory devices having multiple configurations

A memory decoder to decode a memory address targeting a memory device in a memory resource, the memory decoder comprising:

• an input to receive a memory address;
• first selection circuitry to select and output predetermined bits of the memory address as a row address independent of a configuration of a memory device targeted by the memory address;
• configuration determination circuitry to determine the configuration of the memory device targeted by the memory address;
• and
• second selection circuitry to select bits of the memory address as a column address based on the configuration of the memory device targeted by the memory address,
• wherein the first selection circuitry and the configuration determination circuitry are configured concurrently to select the predetermined bits of the memory address as a row address, and to determine the configuration of the memory device targeted by the memory address.

A memory arrangement comprising:

• a memory resource comprising a plurality of memory devices;
• and
• a memory addressing circuit to receive a memory address, to select predetermined bits of the memory address as a row address without utilizing knowledge of a configuration of a memory device addressed by the memory address, to determine the configuration of a memory device addressed by the memory address, and to select bits of the memory address as a column address based on the configuration of the memory device addressed by the memory address,
• wherein the memory addressing circuit is concurrently to select the predetermined bits of the memory as a row address, and to determine the configuration of the memory device addressed by the memory address.

A method of accessing a memory resource including a memory device, the method comprising:

• responsive to receiving a memory address during a memory access cycle, generating a row address utilizing first selection circuitry to select predetermined bits of the memory address as the row address, the selection of the predetermined bits as the row address being performed by the first selection circuitry independent of a configuration of a memory device targeted by the memory address;
• determining the configuration of the memory device targeted by the memory address utilizing configuration determination circuitry, the determination of the configuration of the memory device being determined concurrently with the generation of the row address by the first selection circuitry;
• and
• generating a column address utilizing second selection circuitry to select bits of the memory address as the column address based on the configuration of the memory device, as determined by the configuration determination circuitry.

A memory decoder for decoding a memory address targeting a memory device in a memory resource, the memory decoder comprising:

• first selection means for selecting and outputting predetermined bits of the memory address as a row address without regard to a configuration of the memory device targeted by the memory address;
• configuration determination means for determining the configuration of the memory device targeted by the memory address concurrently with the selection and outputting of the predetermined bits by the first selection means;
• and
• second selection means for selecting bits of the memory address as a column address based on the configuration of the memory device targeted by the memory address.