Multifunctional access devices, systems and methods

A computer graphics system for use with a host computer having a host bus including a host address bus and a host data bus, the system comprising:

• a graphics processor having a local address bus for supplying addresses and a local data bus for supplying data;
• and
• an access circuit including
• an address translator circuit having address inputs for addresses supplied by the host address bus of the host computer and outputs for translated addresses to the local address bus of the graphics processor, the address translator circuit also having registers establishing address segments, said address translator circuit responsive to addresses on the address inputs is the address segments;
• and
• control logic circuitry connected to said address translator circuit and operative to supply a control signal to the graphics processor in response to detection that the address at the address inputs changes from one segment to another segment.

The computer graphics system of claim wherein:

• each of said base registers includes a plurality of least significant bits indicating an address segment size;
• said comparing circuit compares a number of most significant bits of each base register to said address on said host address bus corresponding to said indicated address segment size of said base register;
• and
• said address translator circuit supplying on said local address bus an address including said number of most significant bits from said corresponding map register corresponding to said number of most significant bits of said indicated address segment size of said base register.

A method or operating a computer graphics system having a host computer having a host bus including a host address bus and a host data bus and a graphics processor having a local address bus for supplying addresses and a local data bus for supplying data, the method comprising the steps of:

• storing information in a register circuit defining address segments;
• translating addresses for the host address bus into translated addresses on the local address bus in response to detection that the addresses are in the defined address segments;
• and
• supplying a control signal to said graphics processor in response to detection that the address changes from one segment to another segment.