Apparatus and method using volatile lock and lock-down registers and for protecting memory blocks

An apparatus comprising:

• a non-volatile memory array including a plurality of blocks, one or more blocks of said plurality of blocks being capable of being placed in a locked state or an unlocked state;
• a set of volatile lock registers, each lock register of said set of lock registers coupled to a corresponding block of said one or more blocks, and operable to prevent corresponding blocks from being modified;
• a set of volatile lock-down registers, each lock-down register of said set of lock-down registers being associated with a lock register of said set of volatile lock registers and operable to prevent said corresponding blocks from being modified, and further operable to prevent said set of lock registers to be programmed to allow said corresponding blocks to modified;
• a hardware override line coupled to said set of lock registers and said set of lock-down registers, said hardware override line operable to temporarily disable operation of said set of lock-down registers;
• and
• a command buffer coupled to said set of lock registers and said set of lock-down registers, said command buffer operable to transmit a two-cycle command to each register of both said set of lock registers and said set of lock-down registers, wherein the first cycle comprises a command specifying whether a lock configuration of said non-volatile memory array is to be changed, and the second cycle comprises a command specifying whether a block of said memory array is to be placed in a lock state, an unlocked state, or a locked-down state.