Non-blocking hierarchical cache throttle
AssigneeSun Microsystems, Inc.
InventorsRicky C. Hetherington, Thomas M. Wicki
Life of this patent
Estimating the term…
Loading patent…
AssigneeSun Microsystems, Inc.
InventorsRicky C. Hetherington, Thomas M. Wicki
Estimating the term…
A multi-level cache and method for operation of a multi-level cache generating multiple cache system accesses simultaneously. Each access request includes an address identifying a memory location having data that is a target of the access. A insertion pointer inserts each access request into an entry in a memory scheduling window. Each entry is marked as valid when that entry is ready to be applied to a first cache level. A picker picks valid entries from the memory scheduling window by pointing to the picked entry and applying the address therein to the first cache level. The picking occurs in a free-running mode regardless of whether the accesses hit in the first cache level. A second cache level receives accesses that have missed in the first cache level. A resource monitor in the second cache level determines when a predetermined number of resources are committed to servicing the accesses that have missed in the first cache level. In response to the monitoring step the second cache level generates a stall signal thereby stalling the picking process.
A data cache unit associated with a processor, the data cache unit comprising:
A data cache unit associated with a processor, the data cache unit comprising:
A computer system comprising:
Dependencies are inferred from the claim text.