Method for inhibiting thrashing in a multi-level non-blocking cache system
AssigneeSun Microsystems, Inc.
InventorsRicky C. Hetherington, Sharad Mehrotra, Ramesh Panwar
Life of this patent
Estimating the term…
Abstract
A data cache unit associated with a processor, the data cache unit including a first non-blocking cache receiving a data access from a device in the processor. A second non-blocking cache is coupled to the first non-blocking cache to service misses in the first non-blocking cache. A data return path coupled to the second non-blocking cache couples data returning from the second non-blocking cache to both the first non-blocking cache and the device generating the access to the first non-blocking cache.
Claims12
In a processor that executes coded instructions, a method for operation of a multilevel hierarchical cache memory unit where each cache level is non-blocking, the method comprising the steps of:
- generating a plurality of cache access requests from a lower level device, the access requests including an address identifying a memory location having data that is a target of the access;
- applying the address of each request to a lower cache level in a non-blocking fashion;
- generating a miss when the lower cache level fails to include valid data corresponding to one of the applied addresses;
- servicing the lower cache level miss by requesting data from a higher cache level while continuing to generate access requests;
- and
- returning data from the higher cache level in parallel substantially simultaneously to both the lower cache level and the lower level device generating the cache access such that the returning data is synchronized with a reissue of the access request that generated a miss, wherein the reissued access request is generated subsequent to the cache access request that generated the miss.
A computer system comprising:
- a memory;
- a processor coupled to the memory, the processor further comprising:
- an instruction scheduling unit receiving the coded instructions and issuing the received instruction for execution;
- an instruction execution unit generating data accesses in response to the issued instructions;
- a first non-blocking cache receiving a data access from the instruction execution unit in a non-blocking fashion such that in the event of a miss the first non-blocking cache remains available for subsequent access requests;
- a second non-blocking cache coupled to the first non-blocking cache to service misses in the first non-blocking cache;
- and
- a data return path coupled to the second non-blocking cache coupling data returning from the second non-blocking cache in parallel and substantially simultaneously to both the first non-blocking cache and the instruction execution unit such that the returning data is synchronized with a reissue data access request generated subsequent to the data access request that generated the miss.
A method for operation of a non-blocking cache memory comprising:
- generating a cache access from a lower level device by applying an address to a cache memory, wherein the applied address identifies a cache line within the cache memory that is a target of the cache access;
- generating a miss when the identified cache line fails to include valid data corresponding to the applied address;
- servicing the miss by requesting data from another memory device, wherein the servicing results in returning data to the cache;
- and
- causing the lower level device to reapply the address of the cache access to the cache memory substantially simultaneously with the arrival of the returning data to the cache memory.
Dependencies are inferred from the claim text.